ZADCS146/147

12-Bit, 200ksps, ADC Family

Data Sheet

October 12, 2011

© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0

All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without

the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to

changes without notice.

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1.3.2. Specific Parameters of ZADCS146 versions

Parameter

Symbol Conditions

Min

Typ

Max

Unit

Internal Reference at VREF

VREF Output Voltage

2.480

2.500

2.520

V

VREF Short-Circuit Current

30

mA

VREF Temperature Coefficient

± 30

± 50

ppm/°C

Load Regulation

0 to 0.2mA output load

0.35

mV

Capacitive Bypass at VREF

4.7

µF

Capacitive Bypass at REFADJ

0.047

µF

REFADJ Adjustment Range

 1.5

%

VREF Input Voltage Range

1.0

VDD +

50mV

V

VREF Input Current

VREF = 2.5V

180

215

µA

VREF Input Resistance

11.5

14

k



Shutdown VREF Input Current

0.1

µA

REFADJ Buffer Disable Threshold

VDD-

0.5

V

External Reference at VREF_ADJ

Reference Buffer Gain

2.00

VREF_ADJ Input Current

±80

µA

Full Power Down

VREFADJ Input Current

Full Power-Down mode

0.1

µA

Power Requirements

Positive Supply Voltage

VDD

2.7

5.25

V

Operating Mode ext. VREF

0.85

1.0

mA

Operating Mode int. VREF

1.3

1.4

mA

Fast Power-Down

250

300

Positive Supply Current

ZADCS146

ZADCS147

IDD

VDD=3.6V

Full Power-Down

0.5

4.0

µA

Operating Mode ext. VREF

1.00

1.3

mA

Operating Mode int. VREF

1.40

1.6

mA

Fast Power-Down

250

300

Positive Supply Current

ZADCS146

ZADCS147

IDD

VDD=5.2V

Full Power-Down

0.5

4.0

µA