EM78P458AP datasheet(17/76 Pages) EMC

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EM78P458/459

OTP ROM

• Bit 1 (OD1) Control bit is used to enable the open-drain of the P65 pin.

• Bit 0 (OD0) Control bit is used to enable the open-drain of the P64 pin.

• IOCC0 register is both readable and writable.

8. IOCD0 (Pull-high Control Register)

/PH7

/PH6

/PH5

/PH3

/PH2

/PH1

/PH0

• Bit 7 (/PH7) Control bit is used to enable the pull-high of the P56 pin.

0: Enable internal pull-high;

1: Disable internal pull-high.

• Bit 6 (/PH6) Control bit is used to enable the pull-high of the P55 pin.

• Bit 5 (/PH5) Control bit is used to enable the pull-high of the P53 pin.

• Bit 4 Not used.

• Bit 3 (/PH3) Control bit is used to enable the pull-high of the P63 pin.

• Bit 2 (/PH2) Control bit is used to enable the pull-high of the P62 pin.

• Bit 1 (/PH1) Control bit is used to enable the pull-high of the P61 pin.

• Bit 0 (/PH0) Control bit is used to enable the pull-high of the P60 pin.

• IOCD0 register is both readable and writable.

9. IOCE0 (WDT Control Register)

WDTE

EIS

• Bit 7 (WDTE) Control bit is used to enable Watchdog Timer.

0: Disable WDT;

1: Enable WDT.

WDTE is both readable and writable

• Bit 6 (EIS) Control bit is used to define the function of the P50 (/INT) pin.

0: P50, input pin only;

1: /INT, external interrupt pin. In this case, the I/O control bit of P50 (bit 0 of IOC50) must be set to

"1".

When EIS is "0", the path of /INT is masked. When EIS is "1", the status of /INT pin can also be read

by way of reading Port 5 (R5). Refer to Fig. 7.

EIS is both readable and writable.

• Bits 5~0 Not used.

This specification is subject to change without prior notice.

06.25.2004 (V1.4)

EM78P458AP Datenblatt(PDF) 17 Page - ELAN Microelectronics Corp