IO107PDB1 datasheet(23/210 Pages) MICROSEMI

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ProASIC3 Flash Family FPGAs

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Overview of I/O Performance

Summary of I/O DC Input and Output Levels – Default I/O Software

Settings

Table 2-18 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Advanced I/O Banks

I/O Standard

Drive

Strength

Equiv.

Software

Default

Drive

Strength

Option2

Slew

Rate

VIL

VIH

VOL

VOH

IOL1

IOH1

Min.

Max.

Min.

Max.

Min.

3.3 V LVTTL /

3.3 V

LVCMOS

12 mA

High –0.3

0.8

3.6

0.4

2.4

3.3 V

LVCMOS

Wide Range3

100 µA

12 mA

High –0.3

0.8

3.6

0.2

VCCI – 0.2

0.1

2.5 V

LVCMOS

12 mA

High –0.3

0.7

1.7

2.7

0.7

1.7

1.8 V

LVCMOS

12 mA

High –0.3 0.35 * VCCI 0.65 * VCCI 1.9

0.45

VCCI – 0.45

1.5 V

LVCMOS

12 mA

High –0.3 0.35 * VCCI 0.65 * VCCI 1.6

0.25 * VCCI 0.75 * VCCI

3.3 V PCI

Per PCI specifications

3.3 V PCI-X

Per PCI-X specifications

Notes:

1. Currents are measured at 85°C junction temperature.

2. 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT operate at the

equivalent software default drive strength. These values are for Normal Ranges ONLY.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

IO107PDB1 Datenblatt(PDF) 23 Page - Microsemi Corporation

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