R3 =

- 1

1.8

x R4

LM27342

PVIN

EN

BOOST

SW

FB

GND/DAP

C2

L1

C1

C3

R1

R2

D1

SYNC

AVIN

CLK

R4

R3

LM27341, LM27342, LM27341Q, LM27342Q

www.ti.com

SNVS497D – NOVEMBER 2008 – REVISED FEBRUARY 2010

Figure 35. Resistor Divider on EN

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FREQUENCY SYNCHRONIZATION

The LM27341/LM27342 switching frequency can be synchronized to an external clock, between 1.00 and 2.35

MHz, applied at the SYNC pin. At the first rising edge applied to the SYNC pin, the internal oscillator is

overridden and subsequent positive edges will initiate switching cycles. If the external SYNC signal is lost during

operation, the LM27341/LM27342 will revert to its internal 2 MHz oscillator within 1.5 µs. To disable Frequency

Synchronization and utilize the internal 2 MHz oscillator, connect the SYNC pin to GND.

The SYNC pin gives the designer the flexibility to optimize their design. A lower switching frequency can be

chosen for higher efficiency. A higher switching frequency can be chosen to keep EMI out of sensitive ranges

such as the AM radio band. Synchronization can also be used to eliminate beat frequencies generated by the

interaction of multiple switching power converters. Synchronizing multiple switching power converters will result

in cleaner power rails.

the device.

(7)

regulation, and the current limit is not guaranteed. The switching is in phase but no longer at the same switching

frequency as the SYNC signal.

CURRENT LIMIT

The LM27341 and LM27342 use cycle-by-cycle current limiting to protect the output switch. During each

switching cycle, a current limit comparator detects if the output switch current exceeds 2.0A min (LM27341) or

2.5A min (LM27342) , and turns off the switch until the next switching cycle begins.

FREQUENCY FOLDBACK

The LM27341/LM27342 employs frequency foldback to protect the device from current run-away during output

short-circuit. Once the FB pin voltage falls below regulation, the switch frequency will smoothly reduce with the

falling FB voltage until the switch frequency reaches 220 kHz (typ). If the device is synchronized to an external

clock, synchronization is disabled until the FB pin voltage exceeds 0.53V

SOFT-START

The LM27341/LM27342 has a fixed internal soft-start of 1 ms (typ). During soft-start, the error amplifier’s

reference voltage ramps from 0.0 V to its nominal value of 1.0 V in approximately 1 ms. This forces the regulator

output to ramp in a controlled fashion, which helps reduce inrush current. Upon soft-start the part will initially be

in frequency foldback and the frequency will rise as FB rises. The regulator will gradually rise to 2 MHz. The

LM27341/LM27342 will allow synchronization to an external clock at FB > 0.53V.

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