TSB41AB2IPAP datasheet(39/55 Pages) TI1

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TSB41AB2, TSB41AB2I

IEEE 1394a2000 TWOPORT CABLE

TRANSCEIVER/ARBITER

SLLS424G − JUNE 2000 − REVISED DECEMBER 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

receive (continued)

The sequence of events for a null packet reception is as follows:

Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines.

Normally, the interface is idle until receive is asserted. However, the receive operation may interrupt a status

transfer operation that is in progress so that the CTL lines may change from status to receive without an

intervening idle.

Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles.

Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines.

The PHY asserts at least one cycle of idle following a receive operation.

Table 20. Receive Speed Codes

D0 − D7

DATA RATE

00XX XXXX

S100

0100 XXXX

S200

0101 0000

S400

1YYY YYYY

data-on indication

NOTE: X = Output as 0 by PHY, ignored by LLC.

Y = Output as 1 by PHY, ignored by LLC.

transmit

When the LLC issues a bus request through the LREQ terminal, the PHY arbitrates to gain control of the bus.

If the PHY wins arbitration for the serial bus, the PHY-LLC interface bus is granted to the LLC by asserting the

grant state (11b) on the CTL terminals for one SYSCLK cycle, followed by idle for one clock cycle. The LLC then

takes control of the bus by asserting either idle (00b), hold (01b) or transmit (10b) on the CTL terminals. Unless

the LLC is immediately releasing the interface, the LLC may assert Idle for at most one clock before it must assert

either hold or transmit on the CTL terminals. The hold state is used by the LLC to retain control of the bus while

it prepares data for transmission. The LLC may assert hold for zero or more clock cycles (that is, the LLC need

not assert hold before transmit). The PHY asserts data prefix on the serial bus during this time.

When the LLC is ready to send data, the LLC asserts transmit on the CTL terminals as well as sending the first

bits of packet data on the D lines. A transmit is held on the CTL terminals until the last bits of data have been

sent. The LLC then asserts either hold or idle on the CTL terminals for one clock cycle, and then asserts idle

for one additional cycle before releasing the interface bus and placing its CTL and D terminals in a high-

impedance state. The PHY then regains control of the interface bus.

The hold asserted at the end of packet transmission indicates to the PHY that the LLC requests to send another

packet (concatenated packet) without releasing the serial bus. The PHY responds to this concatenation request

by waiting the required minimum packet separation time and then asserting grant as before. This function may

be used to send a unified response after sending an acknowledge, or to send consecutive isochronous packets

during a single isochronous period. Unless multispeed concatenation is enabled, all packets transmitted during

a single bus ownership must be of the same speed (since the speed of the packet is set before the first packet).

If multi-speed concatenation is enabled (when the EMSC bit of PHY register 5 is set), the LLC must specify the

speed code of the next concatenated packet on the D terminals when it asserts hold on the CTL terminals at

the end of a packet. The encoding for this speed code is the same as the speed code that precedes received

packet data as given in Table 20.

TSB41AB2IPAP Datenblatt(PDF) 39 Page - Texas Instruments

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