TP2540

Features

Low threshold (-2.4V max.)

High input impedance

Low input capacitance (125pF max.)

Fast switching speeds

Low on-resistance

Free from secondary breakdown

Low input and output leakage

Applications

Logic level interfaces - ideal for TTL and CMOS

Solid state relays

Battery operated systems

Photo voltaic drives

Analog switches

General purpose line drivers

Telecom switches

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General Description

This low threshold enhancement-mode (normally-off)

transistor utilizes a vertical DMOS structure and Supertex’s

well-proven silicon-gate manufacturing process. This

combination produces a device with the power handling

capabilities of bipolar transistors and with the high input

impedance and positive temperature coefficient inherent

in MOS devices. Characteristic of all MOS structures,

this device is free from thermal runaway and thermally-

induced secondary breakdown.

Supertex’s vertical DMOS FETs are ideally suited to a wide

range of switching and amplifying applications where very

low threshold voltage, high breakdown voltage, high input

impedance, low input capacitance, and fast switching

speeds are desired.

P-Channel Enhancement Mode

Vertical DMOS FETs

Absolute Maximum Ratings

Product Marking

TO-243AA (SOT-89) (N8)

= “Green” Packaging

GATE

SOURCE

DRAIN

DRAIN

Ordering Information

Device

Package Options

BV

(V)

R

DS(ON)

(max)

(Ω)

V

GS(th)

(max)

(V)

I

D(ON)

(min)

(A)

TO-92

TO-243AA (SOT-89)

Die*

TP2540

TP2540N3-G

TP2540N8-G

TP2540ND

-400

25

-2.4

-0.4

-G indicates package is RoHS compliant (‘Green’)

* MIL visual screening available.

Parameter

Value

Drain-to-source voltage

BV

DSS

Drain-to-gate voltage

BV

DGS

Gate-to-source voltage

±20V

Operating and storage temperature

-55°C to +150°C

Soldering temperature*

+300°C

Absolute Maximum Ratings are those values beyond which damage to the device may

occur. Functional operation under these conditions is not implied. Continuous operation

of the device at the absolute rating level may affect device reliability. All voltages are

referenced to device ground.

*

Distance of 1.6mm from case for 10 seconds.

GATE

SOURCE

DRAIN

TO-92 (N3)

TO-243AA (SOT-89) (N8)

YY = Year Sealed

WW = Week Sealed

= “Green” Packaging

SiTP

2 5 4 0

Y Y W W

TO-92 (N3)

Package may or may not include the following marks: Si or

Package may or may not include the following marks: Si or

Pin Configurations