9

CUE

BL

CLR

CE

1

CE

2

WR

CU

A

1

A

0

D

6

D

5

D

4

D

3

D

2

D

1

D

0

Function

01

1

Display ASCII

11

1

Display Stored Cursor

XX

XXXX

X

XXX

X

X

X

XX

0

Reset RAMs

Blank Display but do not reset

X0

1

RAMS and Control Register

Extended

Intensity

Master

Digit

Digit

Write to Attribute RAM

0

0

0

Functions

Control

Blank

Blank

Cursor

and Control Register

Disable

Disable 0

0

0 =

000 = 100%*

0 =

Digit

Digit

DBD

0

0

1

Enable

001 = 60%

Display

Blank

Cursor

blanked

D

010 = 40%

ON

Disable 1

1

011 = 27%

DBD

X

X

1

0

0

0

1 =

100 = 17%

1 =

Digit

Digit

from being blanked.

0

1

0

Disable

101 = 10%

Display

Blank

Cursor

D

110 = 7%

Blanked

Disable 2

2

DC

111 = 3%

Digit n

D

0

Digiit

Digit

0

1

1

Always

Blank

Cursor

DC

Enabled

Disable 3

3

Digit n

1

0

0

Digit 0 ASCII Data (Right Most Character)

1

0

1

Digit 1 ASCII Data

XX

1

0

0

0

Write to Character RAM

1

1

0

Digit 2 ASCII Data

1

1

1

Digit 3 ASCII Data (Left Most Character)

1X

X

X

X

1

X

1

X

X

X

X

X

X

X

X

X

X

X

No Change

XX

1

Display Clear

Data stored in the Character

RAM, Control Register, and

Attribute RAM will be cleared if

the clear (CLR) is held low for a

minimum of 10

µs. Note that the

display will be cleared regardless

of the state of the chip enables

(CE

1

, CE

2

). After the display is

cleared, the ASCII code for a

space (20hex) is loaded into all

character RAM locations and

00hex is loaded into all Attribute

RAM/Control Register memory

locations.

Data Entry

Figure 2 shows a truth table for

the HDLX-2416 display. Setting

the chip enables (CE

1

, CE

2

) to

logic 0 and the cursor select (CU)

to logic 1 will enable ASCII data

loading. When cursor select (CU)

is set to logic 0, data will be

loaded into the Control Register

and Attribute RAM. Address

inputs A

0

-A

1

are used to select the

digit location in the display. Data

inputs D

0

-D

6

are used to load

information into the display. Data

will be latched into the display on

the rising edge of the WR signal.

D

0

-D

6

, A

0

-A

1

, CE

1

, CE

2

, and CU

must be held stable during the

write cycle to ensure that correct

data is stored into the display.

Data can be loaded into the

display in any order. Note that

when A

0

and A

1

are logic 0, data is

stored in the right most display

location.

Cursor

When cursor enable (CUE) is a

logic 1, a cursor will be displayed

in all digit locations where a logic

1 has been stored in the Digit

Cursor memory in the Attribute

RAM. The cursor consists of all

35 dots ON at half brightness. A

flashing cursor can be displayed

by pulsing CUE. When CUE is a

logic 0, the ASCII data stored in

the Character RAM will be dis-

played regardless of the Digit

Cursor bits.

Blanking

Blanking of the display is con-

trolled through the BL input, the

Control Register and Attribute

RAM. The user can achieve a

variety of functions by using these

controls in different combinations,

such as full hardware display

blank, software blank, blanking of

individual characters, and syn-

chronized flashing of individual

characters or entire display (by

Figure 2. Display Truth Table

0 = Logic 0; 1 = Logic 1; X = Do Not Care; * 000 = 27% for HDLU-2416