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ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]

Atmel-8271IS-AVR- ATmega-Datasheet_10/2014

1.1

Pin Descriptions

1.1.1

VCC

Digital supply voltage.

1.1.2

GND

Ground.

1.1.3

Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output

buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins

that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-

stated when a reset condition becomes active, even if the clock is not running.

Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator amplifier

and input to the internal clock operating circuit.

Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator

amplifier.

If the Internal Calibrated RC Oscillator is used as chip clock source, PB7...6 is used as TOSC2...1 input for the

Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.

1.1.4

Port C (PC5:0)

Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The PC5...0 output

buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins

that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-

stated when a reset condition becomes active, even if the clock is not running.

1.1.5

PC6/RESET

If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics of PC6

differ from those of the other pins of Port C.

If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer than

the minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse length is

1.1.6

Port D (PD7:0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output

buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins

that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-

stated when a reset condition becomes active, even if the clock is not running.