HB7121BELECTRONICS datasheet(12/29 Pages) HYNIX

12 / 29 page

HB7121B

Electronics Industries Co., Ltd.

CMOS IMAGE SENSOR

System IC Division

With 8-bit ADC

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume

any responsibility for use of circuits described. NO patent licenses are implied.

DA21991011R_1.0

- 12 -

1999 Hyundai System IC Division

PRELIMINARY

n Mode B[2] : scr_size(screen size select) <default value : 1b>

Flexible screen size is very useful for customer. If the scr_size is set to high, i.e. window

mode, only pixels in windowed area defined by register 10h ~ 17h can be read . But scr_size

is set to low state, i.e. full screen mode, all pixels in the sensor are read out regardless the

values of register 10h ~ 17h. We can select window mode or full screen mode with this bit. Full

screen size is only for chip test.

- window start point :

x : row start address (register 10h, 11h)

y : column start address (register 12h, 13h)

- window end point :

x : row start address + window width address (register 14h, 15h) - 1

y : column start address + window height address (register 16h, 17h) –1

n Mode B [1] : shot(shot mode) <default value : 0b>

User can select continuous frame mode or snapshot mode according to application.

At the continuous frame mode, pixel data output is updated every VSYNC period. In order to

set snapshot mode, it this bit to ‘ 1’ . In that case, just single frame of pixel data will be read out,

then the sensor stops operation. Snapshot mode can be used for the digital still camera

applications.

n Mode B[0] : int_sel(integration time unit select) <default value : 0b>

This bit defines integration time unit i.e. line base or pixel clock base.

Default mode is line unit integration but at the bright condition or if you need precise exposure

time control, pixel mode is recommended. This bit related to integration time register 25h, 26h,

and 27h.

<Note>

Actual integration time can be calculated using three integration time registers and pixel clock

period.

In pixel mode, integration time = (25h, 26h, 27h) * number of pixel period.

In line mode, integration time = (26h, 27h) * number of pixel per line * pixel period.

(cf) number of pixel per line = 414 + HSYNC duration value

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