PRELIMINARY

                 

               




















































Programmable Divide (N Counter)

The N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the

Control Bits are 10 or 11 (10 for IF counter and 11 for RF counter) data is transferred from the 22-bit shift register into a 4-

bit or 7-bit latch (which sets the Swallow (A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter),

MSB first. Serial data format is shown below. For the IF N counter bits 5, 6, and 7 are don’t care bits. The RF N counter

does not have don’t care bits.

7-Bit Swallow Counter Divide Ratio (A Counter)

RF

DIVIDE

NN

NNN

NN

RATIO A

7

6

543

21

0

0

0

000

00

1

0

0

000

01

•

•

•

•••

••

127

11

111

11

NOTES:

1. Divide ratio 0 to 127

2. B

A

IF

DIVIDE

NN

NNN

NN

RATIO A

7

6

543

21

0

X

X

X

00

00

1

X

X

X

00

01

•

•

•

•••

••

15

X

X

X

1

1

1

1

X = Don’t care condition

11-Bit Programmable Counter Divide Ratio (B Counter)

DIVIDE

NNNNN

NN

N

NNN

RATIO A

1817161514

1312

11

10

9

8

3

00000

00

0

011

4

00000

00

0

100

•

•••

•

•

•••••

•

2047

11111

11

1

111

NOTES:

1. Divide ratio 3 to 2047 (divide ratios less than 3 are prohibited).

2. B

A

Pulse Swallow Function

f

B) + A] f

f

B:

Preset divide ratio of binary 11-bit programmable counter (3 to 2047)

A:

Preset divide ratio of binary 7-bit swallow counter (0

A127 {RF}, 0A15 {IF}, AB)

f

R:

Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767)

P:

Preset modulus of dual modulus prescaler (for IF: P=8 or 16; for RF: P=64 or 128)





































































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