ICS1892 datasheet(92/148 Pages) ICST

92 / 148 page

ICS1892, Rev. D, 2/26/01

February 26, 2001

Chapter 8

Management Register Set

ICS1892 Data Sheet

8.12.5

PLL Lock Error (bit 17.9)

The Phase Locked Loop (PLL) Lock Error bit indicates to an STA whether the ICS1892 has ever

experienced a PLL Lock Error. A PLL Lock Error occurs when a the PLL fails to lock onto the incoming

100Base data stream. If this bit is set to a logic:

• Zero, it indicates that a PLL Lock Error has not occurred since the last read of this register.

• One, it indicates that a PLL Lock Error has occurred after the last read of this register.

This bit is a latching high bit. (For more information on latching high and latching low bits, see Section

8.1.4.1, “Latching High Bits” and Section 8.1.4.2, “Latching Low Bits”.)

Note:

This bit has no definition in 10Base-T mode.

8.12.6

False Carrier (bit 17.8)

The False Carrier bit indicates to an STA the detection of a False Carrier by the ICS1892 in 100Base mode.

A False Carrier occurs when the ICS1892 begins evaluating potential data on the incoming 100Base data

stream, only to learn that it was not a valid /J/K/. If this bit is set to a logic:

• Zero, it indicates that a False Carrier has not been detected since the last read of this register.

• One, it indicates that a False Carrier was detected since the last read of this register.

This bit is a latching high bit. (For more information on latching high and latching low bits, see Section

8.1.4.1, “Latching High Bits” and Section 8.1.4.2, “Latching Low Bits”.)

Note:

This bit has no definition in 10Base-T mode.

8.12.7

Invalid Symbol (bit 17.7)

The Invalid Symbol bit indicates to an STA the detection of an Invalid Symbol in a 100Base data stream by

the ICS1892.

During reception of a valid packet, the ICS1892 examines each Symbol to ensure that the data being

passed to the MAC/Repeater Interface is error free. If an error occurs, the ICS1892 indicates this condition

to the MAC/repeater. An Invalid Symbol occurs when the ICS1892 evaluates a valid packet and finds an

Invalid Symbol in the data.

If this bit is set to a logic:

• Zero, it indicates an Invalid Symbol has not been detected since the last read of this register.

• One, it indicates an Invalid Symbol was detected since the last read of this register.

This bit is a latching high bit. (For more information on latching high and latching low bits, see Section

8.1.4.1, “Latching High Bits” and Section 8.1.4.2, “Latching Low Bits”.)

Note:

This bit has no definition in 10Base-T mode.

ICS1892 Datenblatt(PDF) 92 Page - Integrated Circuit Systems

ICS1892 Datenblatt(HTML) 92 Page - Integrated Circuit Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL