ICS673-01

PLL Building Block

MDS 673-01 D

3

Revision 022500

Printed 11/15/00

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel • www.icst.com

Parameter

Conditions

Minimum

Typical

Maximum

Units

ABSOLUTE MAXIMUM RATINGS (n

note 1)

Supply voltage, VDD

Referenced to GND

7

V

Inputs and Clock Outputs

Referenced to GND

-0.5

VDD+0.5

V

Ambient Operating Temperature

ICS673M-01

0

70

°C

ICS673M-01I

-40

85

°C

Soldering Temperature

Max of 10 seconds

260

°C

Storage temperature

-65

150

°C

DC CHARACTERISTICS (VDD = 5.0 V unless noted)

Operating Voltage, VDD

3.13

5.50

V

Input High Voltage

All except VCOIN

2

V

Input Low Voltage

All except VCOIN

0.8

V

Input High Voltage

VCOIN

VDD

V

Input Low Voltage

VCOIN

0

V

Output High Voltage, VOH

IOH=-25mA

2.4

V

Output Low Voltage, VOL

IOL=25mA

0.4

V

Output High Voltage, VOH, CMOS level

IOH=-8mA

VDD-0.4

V

Operating Supply Current, IDD

No Load,CLK1=40MHz

15

mA

Power Down Supply Current, IDDPD

No Load

6

µA

Short Circuit Current

Each output

±100

mA

Input Capacitance

OE, PD, SEL

5

pF

AC CHARACTERISTICS (VDD = 5.0 V

V unless noted)

Output Clock Frequency (4.5 to 5.5 V)

CLK1 with SEL=1

2

135

MHz

Output Clock Frequency (3.13 to 3.46 V)

CLK1 with SEL=1

2

100

MHz

CLK1 and CLK2 skew

Rising edges at VDD/2

500

ps

Output Clock Rise Time

0.8 to 2.0V

1.5

ns

Output Clock Fall Time

2.0 to 0.8V

1.5

ns

Output Clock Duty Cycle

At VDD/2

45

50

55

%

VCO Gain, Kv

95

MHz/V

Charge Pump Current, Ic

2.4

µA

Electrical Specifications

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged

exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.