ICS673-01

PLL Building Block

MDS 673-01 D

2

Revision 022500

Printed 11/15/00

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel • www.icst.com

Pin Descriptions

Key: CI = clock input, I = Input, O = output, P = power supply connection

Pin Assignment

Number

Name

Type

Description

1

FBIN

CI

FeedBack INput. Connect feedback clock to this pin. Falling edge triggered.

2

VDD

P

VDD. Connect to +3.3 V or +5 V, and to VDD on pin 3.

3

VDD

P

VDD. Connect to VDD on pin 2.

4

GND

P

Connect to ground.

5

GND

P

Connect to ground.

6

GND

P

Connect to ground.

7

CHGP

O

CHarGe Pump output. Connect to VCOIN under normal operation.

8

VCOIN

I

Input to internal VCO.

9

CAP

I

Loop filter return.

10

OE

I

Output Enable. Active high. Tri-states both outputs when low.

11

SEL

I

SELect pin for VCO pre-divide per table above.

12

PD

I

Power Down. Turns off entire chip when this pin is low. Outputs stop low.

13

CLK2

O

CLocK output 2. This is a low-skew divide by two version of CLK1.

14

CLK1

O

CLocK output 1.

15

NC

-

No Connect. Nothing is connected internally to this pin.

16

REFIN

CI

REFerence INput. Connect reference clock to this pin. Falling edge triggered.

VCO Predivide Select Table

16

15

14

13

16 pin narrow (150 mil) SOIC

12

11

10

9

1

2

3

4

5

6

7

8

ICS673-01

VDD

GND

FBIN

VDD

GND

VCOIN

GND

CHGP

OE

CAP

SEL

NC

REFIN

CLK1

CLK2

PD

0 = connect pin directly to ground

1 = connect pin directly to VDD

SEL

VCO Predivide

04

11