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ICS9147F-06 Datenblatt(PDF) 4 Page - Integrated Circuit Systems

Teilenummer ICS9147F-06
Bauteilbeschribung  Frequency Generator & Integrated Buffers for PENTIUMTM
PDF  6 Pages
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Hersteller  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS9147F-06 Datenblatt(HTML) 4 Page - Integrated Circuit Systems

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ICS9147-06
Electrical Characteristics at 3.3V
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
VDDL=VDD3=3.0 – 3.7 V, TA = 0 – 70
° C unless otherwise stated
AC Characteristics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Rise Time
1
Tr1
20pF load, 0.8 to 2.0V
CPU, BUS & REF1
-0.9
1.5
ns
Fall Time
1
Tf1
20pF load, 2.0 to 0.8V
CPU, BUS & REF1
-
0.8
1.4
ns
Rise Time
1
Tr2
20pF load, 20% to 80%
CPU, BUS & REF1
-1.5
2.5
ns
Fall Time
1
Tf2
20pF load, 80% to 20%
CPU, BUS & REF1
-
1.4
2.4
ns
Rise Time
1
Tr1
30pF load, 0.8 to 2.0V
CPU, BUS & REF1
-0.9
1.5
ns
Fall Time
1
Tf1
30pF load, 2.0 to 0.8V
CPU, BUS & REF1
-
0.8
1.4
ns
Rise Time
1
Tr2
30pF load, 20% to 80%
CPU, BUS & REF1
-1.5
2.5
ns
Fall Time
1
Tf2
30pF load, 80% to 20%
CPU, BUS & REF1
-
1.4
2.4
ns
Rise Time
1
Tr3
20pF load, 0.8 to 2.0V
24 & 48 clocks & REF (2:3)
--
-
ns
Fall Time
1
Tf3
20pF load, 2.0 to 0.8V
24 & 48 clocks & REF (2:3)
--
ns
Rise Time
1
Tr4
20pF load, 0.4 to 2.0V , CPU with
VDDL = 2.5V and IOAPIC
-
-
1.6
ns
Fall Time
1
Tf4
20pF load, 2.0 to 0.4V, CPU with
VDDL = 2.5V and IOAPIC
-
-
1.6
ns
Duty Cycle
1
Dt1
20pF load @ VOUT=1.4V
45
50
55
%
Duty Cycle
Dt2
REF (1:3)
40
45
50
%
Jitter, One Sigma
1
Tjis1
CPU & Fixed BUS Load=20pF,
BUS; Load = 30pF
-
50
150
ps
Jitter, Absolute
1
Tjab1
CPU & Fixed BUS Load=20pF,
BUS; Load = 30pF
-250
-
250
ps
Jitter, One Sigma
1
Tjis2
REF1; Load = 47pF
-
55
250
ps
Jitter, Absolute
1
Tjab2
REF1; Load = 47pF
-500
200
500
ps
Input Frequency
1
Fi
12.0
14.318
16.0
MHz
Logic Input Capacitance
1
CIN
Logic input pins
-
5
-
pF
Oscillator Input Capacitance
1
CINX
X1, X2 pins
-
18
-
pF
Power-on Time
1
ton
From VDD=3.0V to 1st crossing of
66.6 MHz VDD supply ramp < 1 ms
-1.5
3.0
ms
Clock Skew
1
Tsk1
CPU to CPU; Load=20pF; @1.4V
(Same VDD)
-
150
250
ps
Clock Skew
1
Tsk2
BUS to BUS; Load=20pF; @1.4V
-
300
500
ps
Clock Skew
1
Tsk3
CPU to BUS; Load=20pF; @1.4V
(CPU is early) (All at 3.3V)
13.3
4
ns
Clock Skew
1
Tsk4
CPU @ 2.5 to CPUH @ 3.3V
Tsk5
CPU @ 2.5V to BUS @ 3.3V
Tsk6
REF @ 3.3V to IOAPIC @ 2.5V



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