2

ICS9248-134

Pin Descriptions

The ICS9248-134 is a main clock synthesizer chip for Pentium II based systems using Rambus Interface DRAMs. This chip

provides all the clocks required for such a system when used with a Direct Rambus Clock Generator(DRCG) chip such as the

ICS9212-01.

Spread Spectrum may be enabled by driving the SPREAD# pin active. Spread spectrum typically reduces system EMI by 8dB

to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-134

employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature

variations.

The CPU/2 clocks are inputs to the DRCG.

General Description

Pin number

Pin name

Type

Description

1, 7, 13, 19, 25, 31,

36, 41, 45

G ND

PWR

G round pins

2

REF0

OU T

14.318M Hz reference clock outputs at 3.3V

REF1

OU T

14.318M Hz reference clock outputs at 3.3V

SEL24_48

IN

Logic input to select 24 or 48M Hz for pin 26 output

4, 10, 16, 23,

28, 35

V DD

PWR

Power pins 3.3V

5

X 1

IN

X TAL_IN 14.318M Hz crystal input

6

X 2

OU T

X TAL_O UT Crystal output

PCICLK_F

OU T

Free running PCI clock at 3.3V . Synchronous to CPU clocks. Not

affected by the PCI_STOP# input.

FS0

IN

Logic - input for frequency selection

PCICLK0

OU T

PCI clock output at 3.3V . Synchronous to CPU clocks.

FS1

IN

Logic - input for frequency selection

PCICLK1

OU T

PCI clock output at 3.3V . Synchronous to CPU clocks.

FS2

IN

Logic - input for frequency selection

PCICLK2

OU T

PCI clock output at 3.3V . Synchronous to CPU clocks.

FS3

IN

Logic - input for frequency selection

14, 15, 17, 18, 20,

21, 22

PCICLK (9:3)

OU T

PCI clock outputs at 3.3V. Synchronous to CPU clocks.

24

PD #

IN

This asynchronous input powers down the chip when drive

active(Low). The internal PLLs are disabled and all the output clocks

are held at a Low state.

26

24_48M Hz

OU T

24 or 48M Hz output selectable by

SEL24_48# (0=48M Hz 1=24M Hz)

48M Hz

OU T

Fixed 48M Hz clock output. 3.3V

FS4

IN

Logic - input for frequency selection

29

SCLK

IN

Clock input of I

30

SD ATA

I/O

Data pin for I

2

C circuitry 5V tolerant

32, 33, 34

3V66 (2:0)

OU T

3.3V clock outputs. These outputs are stopped when CPU_STOP#

is driven active..

37, 38, 40

CPUCLK (2:0)

OU T

H ost bus clock output at 2.5V.

42

CPU/2

OU T

2.5V clock outputs at 1/2 CPU frequency.

39, 43, 48

V DDL

PWR

Power pins for the CPU, CPU/2 & IO APIC clocks. 2.5V

44, 46, 47

IOAPIC (2:0)

OU T

IOAPIC clocks at 2.5V. Synchronous with CPU CLKs.

27

12

3

8

9

11