AD5040/AD5060

Rev. A | Page 7 of 24

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD5040/

AD5060

TOP VIEW

(Not to Scale)

SYNC

18

AGND

SCLK

27

DIN

DACGND

36

45

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

DIN

Serial Data Input. These parts have a 16-/24-bit shift register. Data is clocked into the register on the falling edge of

the serial clock input.

2

3

Reference Voltage Input.

4

Analog Output Voltage from DAC.

5

AGND

Ground Reference Point for Analog Circuitry.

6

DACGND

Ground Input to the DAC Core.

7

SYNC

Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC

goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks.

The DAC is updated following the 16th/24th clock cycle unless SYNC is taken high before this edge, in which case

the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC.

8

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can

be transferred at rates up to 30 MHz.