TS80C186EB13 datasheet(9/59 Pages) INTEL

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80C186EB80C188EB 80L186EB80L188EB

Table 2 Pin Description Nomenclature

Symbol

Description

Power Pin (Apply aVCC Voltage)

Ground (Connect to VSS)

Input Only Pin

Output Only Pin

InputOutput Pin

S(E)

Synchronous Edge Sensitive

S(L)

Synchronous Level Sensitive

A(E)

Asynchronous Edge Sensitive

A(L)

Asynchronous Level Sensitive

H(1)

Output Driven to VCC during Bus Hold

H(0)

Output Driven to VSS during Bus Hold

H(Z)

Output Floats during Bus Hold

H(Q)

Output Remains Active during Bus Hold

H(X)

Output Retains Current State during Bus Hold

R(WH)

Output Weakly Held at VCC during Reset

R(1)

Output Driven to VCC during Reset

R(0)

Output Driven to VSS during Reset

R(Z)

Output Floats during Reset

R(Q)

Output Remains Active during Reset

R(X)

Output Retains Current State during Reset

I(1)

Output Driven to VCC during Idle Mode

I(0)

Output Driven to VSS during Idle Mode

I(Z)

Output Floats during Idle Mode

I(Q)

Output Remains Active during Idle Mode

I(X)

Output Retains Current State during Idle Mode

P(1)

Output Driven to VCC during Powerdown Mode

P(0)

Output Driven to VSS during Powerdown Mode

P(Z)

Output Floats during Powerdown Mode

P(Q)

Output Remains Active during Powerdown Mode

P(X)

Output Retains Current State during Powerdown Mode

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