7-1227

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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CD4532BMS

CMOS 8-Bit Priority Encoder

Pinout

CD4532BMS

TOP VIEW

Functional Diagram

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

D4

D5

D6

D7

EI

Q2

VSS

Q1

VDD

GS

D3

D2

D1

D0

Q0

E0

PRIORITY

SELECT

ENCODER

D7

D0

E1

GS

Q2

Q1

Q0

E0

Features

• High Voltage Type (20V Rating)

• Converts From 1 of 8 to Binary

• Provides Cascading Feature to Handle Any Number of

Inputs

• Group Select Indicates One or More Priority Inputs

• Standardized Symmetrical Output Characteristics

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1

µA at 18V Over Full Pack-

• Noise Margin (Over Full Package/Temperature Range)

- 0.5V at VDD = 5V

- 1.5V at VDD = 10V

- 1.5V at VDD = 15V

• 5V, 10V and 15V Parametric Ratings

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Specifications for Description of

‘B’ Series CMOS Devices”

Applications

• Priority Encoder

• Binary or BCD Encoder (Keyboard Encoding)

• Floating Point Arithmetic

Description

CD4532BMS consists of combinational logic that encodes

the highest priority input (D7 - D0) to a 3-bit binary code. The

eight inputs, D7 through D0, each have an assigned priority;

D7 is the highest priority and D0 is the lowest. The priority

encoder is inhibited when the chip-enable input E1 is low.

When E1 is high, the binary representation of the highest-

priority input appears on output lines Q2 - Q0, and the group

select line GS is high to indicate that priority inputs are

present. The enable-out (EO) is high when no priority inputs

are present. If any one input is high, EO is low and all cas-

caded lower-order stages are disabled.

The CD4532BMS is supplied in these 16-lead outline packages:

Braze Seal DIP

H4T

Frit Seal DIP

H1E

Ceramic Flatpack

H6W

December 1992

File Number

3344