2-6

PARAMETER

TEST CONDITIONS

TEMP.

MIN

TYP

MAX

UNITS

Operating LO Frequency (32/33 Prescaler)

Full

1800

-

2220

MHz

Operating LO Frequency (64/65 Prescaler)

Full

1800

-

3500

MHz

Reference Oscillator Frequency

Full

-

-

50

MHz

Selectable Prescaler Ratios (P)

Full

32/33

-

64/65

-

Swallow Counter Divide Ratio (A Counter)

Full

0

-

127

-

Programmable Counter Divide Ratio (B Counter)

Full

3

-

2047

-

Reference Counter Divide Ratio (R Counter)

Full

3

-

32767

-

Reference Oscillator Sensitivity, Single or Differential

Sine Inputs

Full

0.5

-

Reference Oscillator Sensitivity, CMOS Inputs,

Single Ended or Complimentary

Full

-

CMOS

-

Note 7

Reference Oscillator Duty Cycle

CMOS Inputs

25

40

-

60

%

Charge Pump Sink/Source Current/Tolerance

250

µA Selection ±25%

25

0.18

0.25

0.32

mA

Charge Pump Sink/Source Current/Tolerance

500

µA Selection ±25%

25

0.375

0.50

0.625

mA

Charge Pump Sink/Source Current/Tolerance

750

µA Selection ±25%

25

0.56

0.75

0.94

mA

Charge Pump Sink/Source Current/Tolerance

1mA Selection

±25%

25

0.75

1.0

1.25

mA

Charge Pump Sink/Source Mismatch

Full

-

-

15

%

Charge Pump Output Compliance

Full

0.5

-

V

Charge Pump Supply Voltage

Full

2.7

-

3.6

V

Serial Interface Clock Width

Full

20

-

-

ns

Full

20

-

-

ns

Full

20

-

-

ns

Full

10

-

-

ns

Full

20

-

-

ns

Full

20

-

-

ns

NOTES:

5. The Serial data is clocked on the Rising Edge of the serial clock, MSB first. The serial Interface is active when LE is LOW. The serial Data is

latched into defined registers on the rising edge of LE.

6. As long as power is applied, all register settings will remain stored, including the power down state. The system may then come in and out of the

power down state without requiring the registers to be rewritten.

7. CMOS Reference Oscillator input levels are given in the General Electrical Specification section.

POWER ENABLE TRUTH TABLE

PE1

PE2

PLL_PE

(SERIAL BUS)

STATUS

0

0

1

Power Down State, Registers in Save Mode, Inactive PLL, Active

Serial Interface

1

1

1

Receive State, Active PLL

1

0

1

Transmit State, Active PLL

0

1

1

Inactive Transmit and Receive States, Active PLL, Active Serial

Interface

X

X

0

Inactive PLL, Disabled PLL Registers, Active Serial Interface

NOTE:

8. PLL_PE is controlled via the serial interface, and can be used to disable the synthesizer. The actual synthesizer control is a logic AND function

of PLL_PE and the result of the logic OR function of PE1 and PE2. PE1 and PE2 directly control the power enable functionality of the LO buffers.

HFA3683A