6-6

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Intersil Corporation

P. O. Box 883, Mail Stop 53-204

Melbourne, FL 32902

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EUROPE

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Mercure Center

100, Rue de la Fusee

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FAX: (32) 2.724.22.05

ASIA

Intersil (Taiwan) Ltd.

Taiwan Limited

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Taipei, Taiwan

Republic of China

TEL: (886) 2 2716 9310

FAX: (886) 2 2715 3029

The write cycle is initiated on the falling edge of E (T = 0),

which latches the address information in the on-chip

registers. If a write cycle is to be performed where the output

is not to become active, G can be held high (inactive).

TDVWH and TWHDX must be met for proper device opera-

tion regardless of G. If E and G fall before W falls (read

mode), a possible bus conflict may exist. If E rises before W

rises, reference data setup and hold times to the E rising

edge. The write operation is terminated by the first rising edge

of W (T = 2) or E (T = 3). After the minimum E high time

(TEHEL), the next cycle may begin. If a series of consecutive

write cycles are to be performed, the W line may be held low

until all desired locations have been written. In this case, data

setup and hold times must be referenced to the rising of E.

Typical Performance Curve

-55

-35

-15

5

25

45

65

85

105

125

-12

-11

-10

-9

-8

-7

-6

-5

-4

-3

HM-6516