6-122

Timing Waveforms

The HM-6561/883 Read Cycle is initiated on the falling edge

of E. This signal latches the input address word into on-chip

registers. Minimum address setup and hold times must be

met. After the required hold time, the address lines may

change state without affecting device operation. In order to

read the output data E, S1 and S2 must be low and W must

be high. The output data will be valid at access time

(TELQV).

The HM-6561/883 has output data latches that are con-

trolled by E. On the rising edge of E the present data is

latched and remains latched until E falls. Either or both S1 or

S2 may be used to force the output buffers into a high

impedance state.

(7) TAVEL

(7) TAVEL

(8)

TELAX

HIGH

HIGH Z

PREVIOUS DATA

VALID DATA LATCHED

HIGH Z

(4)

TSHQZ

(4)

TSLQX

(4)

TSHQZ

A

E

DQ

S1, S2

-1

TIME

01

2

3

4

5

REFERENCE

W

VALID

(5) TELEH

(17) TELEL

(6) TEHEL

(6) TEHEL

(1) TELQV

(2) TAVQV

FIGURE 1. READ CYCLE

TRUTH TABLE

TIME

REFERENCE

INPUTS

OUTPUT

FUNCTION

E

S1

WA

DQ

-1

H

H

X

X

Z

Memory Disabled

0

X

H

V

Z

Cycle Begins, Addresses are Latched

1

L

L

H

X

X

Output Enabled

2

L

L

H

X

V

Output Valid

3

L

H

X

V

Output Latched

4

H

H

X

X

Z

Device Disabled, Prepare for Next Cycle (Same as -1)

5

X

H

V

Z

Cycle Ends, Next Cycle Begins (Same as 0)

NOTE: 1. Device selected only if both S1 and S2 are low, and deselected if either S1 or S2 are high.

HM-6561/883