ICL7109CPL datasheet(21/25 Pages) INTERSIL

21 / 25 page

Handshake Mode Interfacing

The handshake mode allows ready interface with a wide

variety of external devices. For instance, external latches

may be clocked by the rising edge of CE/LOAD, and the byte

enables may be used as byte identification flags or as load

enables.

Figure 19 shows a handshake interface to Intel microproces-

sors again using an 8255PPI. The handshake operation with

the 8255 is controlled by inverting its Input Buffer Full (IBF)

flag to drive the SEND input to the ICL7109, and using the

CE/LOAD to drive the 8255 strobe. The internal control reg-

ister of the PPI should be sent in MODE 1 for the port used.

If the ICL7109 is in handshake mode and the 8255 IBF flag

is low, the next word will be strobed into the port. The strobe

will cause IBF to go high (SEND goes low), which will keep

the enable byte outputs active. The PPI will generate an

interrupt which when executed will result in the data being

read. When the byte is read, the IBF will be reset low, which

causes the ICL7109 to sequence into the next byte. This fig-

ure shows the MODE input to the ICL7109 connected to a

control line on the PPI. If this output is left high, or tied high

separately, the data from every conversion (provided the

data access takes less time than a conversion) will be

sequenced in two bytes into the system.

If this output is made to go from low to high, the output

sequence can be obtained on demand, and the interrupt

may be used to reset the MODE bit. Note that the

RUN/HOLD input to the ICL7109 may also be obtained on

command under software control. Note that one port of the

8255 is not used, and can service another peripheral device.

the same arrangement can also be used with the 8155.

Figure 20 shows a similar arrangement with the MC6800 or

MCS650X microprocessors, except that both MODE and

RUN/HOLD are tied high to save port outputs.

The handshake mode is particularly convenient for directly

interfacing to industry standard UARTs (such as the Intersil

IM6402 or Western Digital TR1602) providing a minimum

component count means of serially transmitting converted

data. A typical UART connection is shown in Figure 1A. In

this circuit, any word received by the UART causes the

UART DR (Data Ready) output to go high. This drives the

MODE input to the ICL7109 high, triggering the ICL7109 into

handshake mode. The high order byte is output to the UART

first, and when the UART has transferred the data to the

Transmitter Register, TBRE (SEND) goes high again, LBEN

will go high, driving the UART DRR (Data Ready Reset)

which will signal the end of the transfer of data from the

ICL7109 to the UART.

Figure 21 shows an extension of the one converter one

UART scheme to several ICL7109s with one UART. In this

circuit, the word received by the UART (available at the RBR

outputs when DR is high) is used to select which converter

will handshake with the UART. With no external compo-

nents, this scheme will allow up to eight ICL7109s to inter-

face with one UART. Using a few more components to

decode the received word will allow up to 256 converters to

be accessed on one serial line.

MC6820

GND

MODE

ICL7109

B9 - B12

POL, OR

B1 - B8

STATUS

RUN/HOLD

LBEN

HBEN

LOAD

CE/

GND

ANALOG

PA0 - 5

PB0 - 7

CB1

CB2

CRB - -11R-01

MC680X

MCS650X

ADDRESS

BUS

DATA

BUS

CONTROL

BUS

FIGURE 16. FULL-TIME PARALLEL INTERFACE TO MC680X OR MCS650X MICROPROCESSORS

ICL7109

ICL7109CPL Datenblatt(PDF) 21 Page - Intersil Corporation

ICL7109CPL Datenblatt(HTML) 21 Page - Intersil Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

Datenblatt Download

Link URL