AN4369

Impact of the Rs1 and Rs2 mismatch

DocID025335 Rev 1

9/14

5

Impact of the Rs1 and Rs2 mismatch

When adding the external resistances Rsi, it is necessary to fine-tune the gain. This is

because the input bias current is the same on pin+ and pin- and it is extremely important to

have the same resistances connected to the Vn and Vp pins so as to avoid creating a big

equivalent input offset voltage. However, due to the precision of the external resistors this

equivalent offset exists as shown in the equation below:

So,

Where: εβ is the precision of the added serial resistances Rsi.

Example:

R1 = R2 = 5 kΩ

R3 = 100 kΩ

Iib = 15 µA

In the following table, the gain of the TSC product is 20 V/V, 50 V/V, or 100 V/V. It has

been fine-tuned thanks to the Rsi resistances (whose precision is 1 %). The calculus of the

Vout offset has taken into account a process variation of 20 % on the internal resistors

which possibly contribute to a higher gain.

Table 2: Vout offset at different gain vs. series resistances Rsi

Rs1+2

(Ω)

Rs1

(Ω)

Rs2

(Ω)

Equivalent

Vio (V)

Vout offset (V)

with G = 20

Vout offset (V)

with G = 50

Vout offset (V)

with G = 100

50

50.5

0

7.58E-04

1.50E-02

3.76E-02

7.51E-02

49.5

1.50E-05

2.97E-04

7.44E-04

1.49E-03

100

101

0

1.52E-03

2.98E-02

7.45E-02

1.49E-01

99

3.00E-05

5.90E-04

1.48E-03

2.95E-03

200

202

0

3.03E-03

5.86E-02

1.47E-01

2.93E-01

198

6.00E-05

1.16E-03

2.90E-03

5.80E-03

500

505

0

7.58E-03

1.40E-01

3.49E-01

6.99E-01

495

1.50E-04

2.77E-03

6.92E-03

1.38E-02

1000

1010

0

1.52E-02

2.59E-01

6.48E-01

1.30E+00

990

3.00E-04

5.14E-03

1.28E-02

2.57E-02

To this equivalent Vio, the Vio of the TSC itself should be added. Error in gain and

temperature seen in previous parts of this document should also be considered.