AN2021 datasheet(23/39 Pages) STMICROELECTRONICS

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AN2021

New features

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bits (Byte Low of XIRxSEL register). Note that the flag bit can provide information about

events which are not currently serviced by the interrupt controller (since masked through the

enable bits), allowing an effective software management also in the absence of the

possibility to serve the related interrupt request: a periodic polling of the flag bits may be

implemented inside the user application.

Table 13: X-Interrupt detailed mapping gives an overview of the different settings available.

2.3.1

Hardware impact

None.

2.3.2

Software impact

First, the XMISCEN bit, that is, bit 10 of the XPERCON register, must be set to have access

to these registers. Refer to Section 3.1: XPERCON register for more details.

Then, the XIRxSEL registers must be configured. If none of the new XPeripherals is used,

that is, only the XPeripherals that were already present on the ST10F269 are used, the

following values must be programmed:

●

XIR0SEL = 0x0100, only the CAN1 interrupt is enabled and can generate an interrupt

to the ST10 through XP0IC

●

XIR1SEL = 0x0100, only the CAN2 interrupt is enabled and can generate an interrupt

to the ST10 through XP1IC

●

XIR2SEL = 0x0, not used

●

XIR3SEL = 0x2000, only the PLL unlock interrupt is enabled and can generate an

interrupt to the ST10 through XP3IC

Table 13.

X-Interrupt detailed mapping

XP0INT

XP1INT

XP2INT

XP3INT

CAN1 Interrupt

CAN2 Interrupt

I2C Receive

I2C Transmit

I2C Error

SSC1 Receive

SSC1 Transmit

SSC1 Error

ASC1 Receive

ASC1 Transmit

ASC1 Transmit Buffer

ASC1 Error

PLL Unlock / OWD

PWM1 Channel 3...0

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