AN2115 datasheet(13/33 Pages) STMICROELECTRONICS

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AN2115

Operation description

Doc ID 11165 Rev 5

13/33

Figure 9.

Equivalent circuit for voltage loop analysis

To complete the power stage analysis, the zero due to the output capacitor ESR should be

considered.

Equation 1

In Equation 1 the power stage transfer function is shown, where RO is the output equivalent

resistor load (Vo/Io). It can be observed that the pole due to the output capacitor shifts in

frequency based on the load value.

In order to have zero DC error regulation, the feedback voltage loop is implemented with an

integrator stage, the transfer function of which is shown in Equation 2.

Equation 2

where gm is the integrator transconductance (250 µS). The total gain loop is:

Equation 3

where AV is the current loop factor (1 Ω typ.) and α is the resistor feedback network partition

(R2/(R2+R3). Equation 3 does not consider the poles due to the sampling effect which are

placed at half of the switching frequency.

Once the gain loop is known, the system will be stabilized with the compensation network as

shown in the Section 6.1.4.

()

o s

()

L s

()

---------------

oESR

()R

o ESR

() 1

----------------------------------------------------

()

mα

-----------

CRC

-----------------------------

⎝⎠

⎛⎞

•

LOOP s

()

ogmα 1sESRCo

() sC

CRC

()

VsCC 1sCo ESR

()

--------------------------------------------------------------------------------------------

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