AN594 datasheet(21/28 Pages) STMICROELECTRONICS

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Direct LCD Drive

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ANNEX 2: Software of the ST6265x based application (Continued)

ret

;***********************************************************************

END OF MAIN INITIALIZATION

;***********************************************************************

;************************************************************************

MAIN TASK EXAMPLE : ACQUISITION OF USER SPEED REFERENCE DUTY0

duty0 is a user reference that can vary from 0 to 255d

;************************************************************************

DUTY0

jrr

2,pb,slower

; if PB2=0,then slower ; priority on slower

jrr

3,pb,faster

; if PB3=0,then faster ; else continue

ret

; if PB2 & PB3 are high; then continue

slower

a,duty0

cpi

a,000h

jumpz retour

a,counter1

addi

a,01h

counter1,a

jumpnc retour

dec

duty0

; increment duty cycle

ret

faster

a,duty0

cpi

a,0ffh

jrz

retour

a,counter1

addi

a,01h

counter1, a

jrnc

retour

inc

duty0

; decrement duty cycle

retour

ret

;***********************************************************************

end subroutine get_dut0

;***********************************************************************

DUPLEXED LCD DRIVER INTERRUPT SUBROUTINE

task :

generate alternative signals of LCD backplanes control

drive the segments of LCD through port a

calculate duration of each LCD phase

;***********************************************************************

LCD_LP

ldi

wdt,0ffh

; hello watchdog

;

AUX1, a

; |

;

a, x

; | save context of main task (if needed)

;

AUX3, a

; |

;

ldi

tscr1,00h

; timer stop (if needed)

ldi

tcr1 , FASTIM ; LCD phase duration calculation

ldi

tscr1, 07fh

; timer initialization

;************************************************************************

;* LCD phase generation can be here synchronized by other clock system.

for instance : mains voltage synchronization or external clock

;************************************************************************

jrr

0,LCDCTL,LOOP1

; determine phase1 operation

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