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INTERRUPT HANDLING FOR STR7 MICROCONTROLLERS

EIC_INIT

LDR

r3, =EIC_Base_addr

; Read the EIC base address

LDR

r4, =0xE59F0000

; Read the MSB of the LDR pc,[pc,#offset] opcode

STR

r4, [r3, #IVR_off_addr]; Write the MSB of the LDR pc,[pc,#offset]

; instruction code in IVR[31:16]

; The LDR pc,[pc,#offset] opcode

; is : 0xE59FFxxx, with xxx the

; offset to the address pointing

; the interrupt handler.

; the LSB (Fxxx) will be computed and

; placed in to SIRn[31:16] registers

LDR

r5, =SIR0_off_addr

; Read SIR0 address

LDR

r0, =T0TIMI_Addr

; Read the start address of the IRQs

; address table. The IRQ handlers

; located ibelow the exception vectors,

; All addresses are 32bit long

LDR

r1, =0x00000FFF

AND

r0,r0,r1

SUB

r4,r0,#8

; subtract 8 for prefetch,

LDR

r1, =0xF7E8

; add the offset to the 0x00000000

; address(IVR address + 7E8 = 0x00000000)

; 0xFxxx used to complete the

; LDR pc,[pc,#offset] opcode

LDR

r2, =32

; 32 Channel to initialize

ADD

r1,r4,r1

; compute the jump offset

EIC_INI MOV

r4, r1, LSL #16

; Left shift the result

STR

r4, [r3, r5]

; Store the result in SIRx register

ADD

r1, r1, #4

; Next IRQ address

ADD

r5, r5, #4

; Next SIR

SUBS

r2, r2, #1

; Decrement the number of SIR registers

; to initialize

BNE

EIC_INI

; If more then continue

...

Note: In order to run the examples attached to this application note, the STR71x RAM should be mapped

to address 0x00000000.