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UM0225

3 Designing with CAPS

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Appendix B Project Report

This is an example of a project report.

The report includes:

•

CAPS version, project name, location, description and target device

•

Design entry settings and configuration specifications

•

Peripheral/pin assignment

Sample report:

****************************************************************************

* Project file generated by CAPS Version x.xx - 3/20/2006 15:32:08

* Project Name

: Example

* Project Folder

: C:\uPSDsoft\Projects\Example

* Project Description

: This is an example

* Target Device

: STR912FW44X6

****************************************************************************

Voltage

=======

VDDQ LVD threshold voltage : 2.7 V

LVD reset option

: VDD or VDDQ

LVD warning option

: VDD or VDDQ

------------------------------------------------------------------------------

Clocks

======

Master clock source

: PLL

Main crystal frequency

: 25000000.00 Hz

Master clock frequency

: 96000000.00 Hz

M value of PLL

: 25

N value of PLL

: 192

P value of PLL

: 2

RClk divisor value

: 4

RClk frequency

: 24000000.00 Hz

HClk divisor value

: 1

HClk frequency

: 24000000.00 Hz

PClk divisor value

: 2

PClk frequency

: 12000000.00 Hz

FMI divisor value

: 1

FMI CLK frequency

: 24000000.00 Hz

------------------------------------------------------------------------------

Additional Setting

==================

At power up, CPU boot from

: Main Flash

JTAG user code

: 24689ADC

Device Security Protection

: Off

Sector Protection :

Main Flash

Protection Status

----------

-----------------

Sector 0

protected

Sector 1

unprotected

Sector 2

unprotected

Sector 3

unprotected

Sector 4

unprotected

Sector 5

unprotected

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