LTC3421 datasheet(6/16 Pages) LINER

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LTC3421

3421f

PI FU CTIO S

RT (Pin 5): Connect a resistor to ground to program the

oscillator frequency according to the formula:

OSC

28 100

where fOSC is in kHz and RT is in kΩ.

SS (Pin 6): Soft-Start Pin. Connect a capacitor from this

pin to ground to set the soft-start time according to the

formula:

t(ms) = CSS(µF) • 320

The nominal soft-start charging current is 2.5

µA. The

active range of SS is from 0.8V to 1.6V.

SYNC (Pin 7): Oscillator Synchronization Pin. A clock

pulse width of 100ns to 2

µs is required to synchronize the

internal oscillator. If not used SYNC should be grounded.

ILIM (Pin 8): Current Limit Adjust Pin. Connect a resistor

from this pin to ground to set the peak current limit thresh-

old for the N-channel MOSFET according to the formula

(note that this is the peak current in the inductor):

LIM =

150

where I is in amps and R is in k

Ω.

BURST (Pin 9): Burst Mode Threshold Adjust Pin. A

resistor/capacitor combination from this pin to ground

programs the average load current at which automatic

Burst Mode operation is entered, according to the formula:

BURST

where RBURST is in kΩ and IBURST is in amps.

BURST

OUT

≥

•

10 000

where CBURST(MIN) and COUT are in µF.

For manual control of Burst Mode operation, ground the

BURST pin to force Burst Mode operation or connect it to

VOUT to force fixed frequency PWM mode. Note that the

BURST pin must not be pulled higher than VOUT.

GND (Pin 10): Signal Ground Pin. Connect to ground plane

near the RT resistor, error amp compensation compo-

nents and feedback divider.

PGND (Pins 11 to 13): Source Terminal of Power Internal

N-Channel MOSFET.

SW (Pins 14 to 16): Switch Pin for Inductor Connection.

For applications where VOUT > 4.3V, a Schottky diode from

SW to VOUT or to a snubber circuit is required to maintain

absolute maximum rating for SW. (see Application Cir-

cuits for 5V).

VOUT (Pins 17, 19 and 20): The output of the synchronous

rectifier and bootstrapped power source for the IC. A

ceramic bypass capacitor is required to be very close to

the VOUT and PGND pins of the IC.

VOUTS (Pin 18): VOUT Sense Pin. Connect VOUTS directly to

an output filter capacitor. The top of the feedback divider

network should also be tied to this point.

VIN (Pin 21): Input Supply Pin. Connect this pin to the

input supply and decouple with at least a 4.7

µF ceramic

capacitor.

LBO (Pin 22): Open-Drain Output. This pin pulls low when

the LBI input is below 0.6V. The open-drain output can

sink up to 20mA. During Burst Mode operation LBO is only

active during the time the IC wakes up to service the

output.

LBI (Pin 23): Low-Battery Comparator Input. Typical

threshold voltage is 0.6V with 30mV hysteresis. This

function is enabled when the ENB pin is high. The low-

battery comparator will operate off VIN or VOUT, whichever

is greater.

VC (Pin 24): Error Amp Output. A frequency compensation

network is connected from this pin to ground to compen-

sate the loop. See the section Compensating the Feedback

Loop for guidelines.

Exposed Pad (Pin 25): Ground. This pin must be soldered

to the PCB and is typically connected through the power

GND plane.

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