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LT1113

APPLICATI

I FOR ATIO

Typical performance of the instrumentation amplifier:

Input offset voltage = 0.8mV

Input bias current = 320pA

Input offset current = 10pA

Input resistance = 1011

Ω

Input noise = 3.4

µVP-P

High Speed Operation

The low noise performance of the LT1113 was achieved by

making the input JFET differential pair large to maximize

the first stage gain. Increasing the JFET geometry also

increases the parasitic gate capacitance, which if left

unchecked, can result in increased overshoot and ringing.

When the feedback around the op amp is resistive (RF),

a pole will be created with RF, the source resistance and

capacitance (RS,CS), and the amplifier input capacitance

(CIN = 27pF). In closed loop gain configurations and

with RS and RF in the kilohm range (Figure 5), this pole

can create excess phase shift and even oscillation.

A small capacitor (CF) in parallel with RF eliminates this

problem. With RS(CS + CIN) = RFCF, the effect of the

feedback pole is completely removed.

Figure 5.

The concepts of common mode and power supply

rejection ratio match (

∆CMRR and ∆PSRR) are best

demonstrated with a numerical example:

Assume CMRRA = +50µV/V or 86dB,

and CMRRB = + 39µV/V or 88dB,

then

∆CMRR = 11µV/V or 99dB;

if CMRRB = -39µV/V which is still 88dB,

then

∆CMRR = 89µV/V or 81dB

Clearly the LT1113, by specifying and guaranteeing all of

these matching parameters, can significantly improve the

performance of matching-dependent circuits.

Figure 4. Three Op Amp Instrumentation Amplifier

OUTPUT

50pF

10k

1113 • F04

GAIN =

BANDWIDTH =

INPUT REFERRED NOISE =

WIDEBAND NOISE DC TO 400kHz =

CL ≤

100

400kHz

6.6nV/

√Hz AT 1kHz

6.6

µVRMS

0.01

µF

IN–

15V

–15V

–

1/2

LT1113

IC1

1/2

LT1113

IC1

IN+

200

Ω

1/2

LT1113

IC2

1113 • F05

OUTPUT

CIN

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