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LT1306

where

Maximum Load

Output Voltage

Maximum DC Load Current

Maximum Converter Duty Cycle

MAX

IN MIN

–.

()

There is also a second pole at the current loop crossover

frequency

ωC (Figure 6). ωZ is much lower in frequency

than

ωC.Theloopiscompensatedbyadjustingthemidband

gain with resistor R3 (Figure 7) so that the overall loop gain

crosses 0dB before the minimum frequency RHP zero

(i.e., corresponding to the highest duty ratio). The value of

R3 can be estimated with the fromula:

C R

MAX

O L

390

(–

)

Due to the low transconductance of the error amplifier, the

gain setting resistor R3 is AC-coupled with capacitor CZ.

This prevents R3 from inducing an offset to the input of the

error amplifier. It also creates a pole at DC and a low

frequency zero.

The amplitude response of the error amplifier with the

compensation network shown is:

••

•

S R









()

[]

APPLICATIONS INFORMATION

The low frequency zero 1/R3CZ of the compensation

network is placed at

ωP/2.

The capacitor CP ensures adequate gain margin beyond

the RHP zero. The high frequency pole 1/R3CP of the

amplifier frequency response is placed beyond

ωZ.

Higher output filter capacitance rolls off the gain response

from a lower corner frequency so higher midband gain is

required in the compensation network to make the overall

loop gain cross 0dB just below

ωZ.

Layout Consideration

To minimize EMI and high frequency resonances, it is

essential to keep the SW and the CAP trace leads as short

as possible. The input and the output bypass capacitors

CIN and COUT should be placed close to the IC package and

soldered to the ground plane. A ground plane under the

switching regulator is highly recommended. Figure 8

shows a suggested component placement and PC board

layout.

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