LT1376CS datasheet(15/28 Pages) LINER

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LT1375/LT1376

APPLICATIONS INFORMATION

–

2.38V

0.4V

GND

VSW

LT1375/LT1376

INPUT

RFB

RHI

1375/76 F04

OUTPUT

SHDN

STANDBY

TOTAL

SHUTDOWN

3.5

µA

RLO

Figure 4. Undervoltage Lockout

or latch low under low source voltage conditions. UVLO

prevents the regulator from operating at source voltages

where these problems might occur.

Threshold voltage for lockout is about 2.38V, slightly less

than the internal 2.42V reference voltage. A 3.5

µA bias

current flows

out of the pin at threshold. This internally

generated current is used to force a default high state on

the shutdown pin if the pin is left open. When low shut-

down current is not an issue, the error due to this current

can be minimized by making RLO 10k or less. If shutdown

current is an issue, RLO can be raised to 100k, but the error

due to initial bias current and changes with temperature

should be considered.

()

−

()

−

()

238

3 5

to 100k 25k suggested

.. µ

VIN = Minimum input voltage

Keep the connections from the resistors to the shutdown

pin short and make sure that interplane or surface capaci-

tance to the switching nodes are minimized. If high resis-

tor values are used, the shutdown pin should be bypassed

with a 1000pF capacitor to prevent coupling problems

from the switch node. If hysteresis is desired in the

undervoltage lockout point, a resistor RFB can be added to

the output node. Resistor values can be calculated from:

V V

OUT

−+

()+

[]

−

()

()(

)

238

2 35

∆∆

∆

25k suggested for RLO

VIN = Input voltage at which switching stops as input

voltage descends to trip level

∆V = Hysteresis in input voltage level

Example: output voltage is 5V, switching is to stop if input

voltage drops below 12V and should not restart unless

input rises back to 13.5V.

∆V is therefore 1.5V and VIN =

12V. Let RLO = 25k.

−+

()+

[]

−

()

()=

25 12 2 38 1 5 5 1

1 5

238 25 3 5

25 10 41

229

114

114 5 1 5

380

.. /

SWITCH NODE CONSIDERATIONS

For maximum efficiency, switch rise and fall times are

made as short as possible. To prevent radiation and high

frequency resonance problems, proper layout of the com-

ponents connected to the switch node is essential. B field

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