LT1533CS datasheet(5/20 Pages) LINER

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LT1533

PIN FUNCTIONS

GND (Pin 9): Signal Ground. The internal error amplifier,

negative feedback amplifier, oscillator, slew control cir-

cuitry and the bandgap reference are referred to this

ground. Keep the connection to the feedback divider and

VC compensation network free of large ground currents.

VC (Pin 10): The compensation pin is used for frequency

compensation and current limiting. It is the output of the

error amplifier and the input of the current comparator.

Loop frequency compensation can be performed with an

RC network connected from the VC pin to ground.

SHDN (Pin 11): The shutdown pin is used for disabling the

switcher. Grounding this pin will disable all internal cir-

cuitry. Normally this output can be tied high (to VIN) or may

be left floating.

RCSL (Pin 12): A resistor to ground sets the current slew

rate for the collectors A and B. The minimum resistor value

is 3.9k and the maximum value is 68k. Current slew will be

approximately:

ISLEW(A/µs) = 33/RCSL(kΩ)

RVSL (Pin 13): A resistor to ground sets the voltage slew

rate for the collectors A and B. The minimum resistor value

is 3.9k and the maximum value is 68k. Voltage slew will be

approximately:

VSLEW(V/µs) = 220/RVSL(kΩ)

VIN (Pin 14): Input Supply Pin. Bypass this pin with a

≥ 4.7µF low ESR capacitor. When VIN is below 2.55V the

part will go into undervoltage lockout where it will stop

output switching and pull the VC pin low.

PGND (Pin 16): Power Switch Ground. This ground comes

from the emitters of the power switches. In normal opera-

tion this pin should have approximately 25nH inductance

to ground. This can be done by trace inductance (approxi-

mately 1") or with wire or a specific inductive component.

This inductance ensures stability in the current slew

control loop during turn-off. Too much inductance (>50nH)

may produce oscillation on the output voltage slew edges.

COL A, COL B (Pins 2, 15): These are the output collectors

of the power switches. Their emitters return to PGND

through a common sense resistor. COL A and

COL B are alternately turned on out of phase. Large

currents flow into these pins so it is desirable to keep

external trace lengths short to minimize radiation. The

collectors can be tied together for simple boost applica-

tions.

DUTY (Pin 3): Tying the DUTY pin to ground will force the

outputs to switch with a 50% duty cycle. The DUTY pin

must float if not used.

SYNC (Pin 4): The SYNC pin can be used to synchronize

the oscillator to an external clock (see Oscillator Sync in

Applications Information section for more details). The

SYNC pin may either be floated or tied to ground if not

used.

CT (Pin 5): The oscillator capacitor pin is used in conjunc-

tion with RT to set the oscillator frequency. For RT = 16.9k,

CT(NF) = 129/fOSC(kHz)

RT (Pin 6): The oscillator resistor pin is used to set the

charge and discharge currents of the oscillator capacitor.

The nominal value is 16.9k. It is possible to adjust this

resistance

±25% to get a more accurate oscillator fre-

quency.

FB (Pin 7): The feedback pin is used for positive voltage

sensing and oscillator frequency shifting during start-up

and short-circuit conditions. It is the inverting input to the

error amplifier. The noninverting input of this amplifier

connects internally to a 1.25V reference. This pin should

be left open if not used.

NFB (Pin 8): The negative voltage feedback pin is used for

sensing a negative output voltage. The pin is connected to

the inverting input of the negative feedback amplifier

through a 100k source resistor. The negative feedback

amplifier provides a gain of – 0.5 to the feedback amplifier.

The nominal regulation point would be – 2.5V on NFB. This

pin should be left open if not used.

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