LPR520 datasheet(1/5 Pages) LODEV

Teilenummer	LPR520

Bauteilbeschribung	4 x 16-bit Multilevel Pipeline Register

PDF	5 Pages

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Hersteller	LODEV [LOGIC Devices Incorporated]

Direct Link	http://www.logicdevices.com

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DEVICES INCORPORATED

LPR520

4 x 16-bit Multilevel Pipeline Register

Pipeline Registers

08/02/2000–LDS.P520-C

1

u

u Four 16-bit Registers

u

u Implements Double 2-Stage

Pipeline or Single 4-Stage Pipeline

Register

u

u Hold, Shift, and Load Instructions

u

u Separate Data In and Data Out Pins

u

u High-Speed, Low Power CMOS

Technology

u

u Three-State Outputs

u

u 44-pin PLCC, J-Lead

FEATURES

DESCRIPTION

LPR520

4 x 16-bit Multilevel Pipeline Register

DEVICES INCORPORATED

The LPR520 is functionally compat-

ible with the L29C520 but have 16-bit

inputs and outputs. The LPR520 is

implemented in low power CMOS.

The LPR520 contains four registers

which can be configured as two

independent, 2-level pipelines or as

one 4-level pipeline.

The Instruction pins, I1-0, control the

loading of the registers. The registers

may be configured as a four-stage

delay line, with data loaded into R1

and shifted sequentially through R2,

R3, and R4. Also, data may be loaded

from the inputs into either R1 or R3

with only R2 or R4 shifting. Finally,

I1-0 may be set to prevent any register

from changing.

The S1-0 select lines control a 4-to-1

multiplexer which routes the contents

of any of the registers to the Y output

pins. The independence of the I and S

controls allows simultaneous write

and read operations on different

registers.

S1 S0

Register Selected

L

Register 4

L

H

Register 3

H

L

Register 2

H

Register 1

TABLE 2.

OUTPUT SELECT

I1

I0

Description

LL

D©R1

R1©R2

R2©R3

R3©R4

L

H

HOLD

D©R3

R3©R4

HL

D©R1

R1©R2

HOLD

H

ALL REGISTERS ON HOLD

TABLE 1.

LPR520 INSTRUCTION TABLE

LPR520 BLOCK DIAGRAM

REG 1

REG 2

REG 3

REG 4

D15-0

16

OE

Y15-0

S1-0

I1-0

CLK

2

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