__________Applications Information

Power-On Reset

At power-up, the internal power-on reset circuitry sets

INT high and puts the device in normal operation/exter-

nal clock mode. This state is selected to keep the inter-

nal clock from loading the external clock driver when

the part is used in external clock mode.

Internal or External Reference

The MAX196/MAX198 can operate with either an inter-

nal or external reference. An external reference can be

connected to either the REF pin or the REFADJ pin

(Figure 9).

To use the REF input directly, disable the internal buffer

nates the need to buffer the reference externally. When

the reference is applied at REFADJ, bypass REFADJ with

a 0.01µF capacitor to AGND.

The REFADJ internal buffer gain is trimmed to 1.6384 to

provide 4.096V at the REF pin from a 2.5V reference.

Internal Reference

The internally trimmed 2.50V reference is gained

through the REFADJ buffer to provide 4.096V at REF.

Bypass the REF pin with a 4.7µF capacitor to AGND

and the REFADJ pin with a 0.01µF capacitor to AGND.

The internal reference voltage is adjustable to ±1.5%

(±65 LSBs) with the reference-adjust circuit of Figure 1.

External Reference

At REF and REFADJ, the input impedance is a mini-

mum of 10k

Ω for DC currents. During conversions, an

external reference at REF must be able to deliver

400µA DC load currents, and must have an output

impedance of 10

Ω or less. If the reference has higher

output impedance or is noisy, bypass it close to the

REF pin with a 4.7µF capacitor to AGND.

With an external reference voltage of less than 4.096V

at the REF pin or less than 2.5V at the REFADJ pin, the

increase in the ratio of the RMS noise to the LSB value

(FS / 4096) results in performance degradation (loss of

effective bits).

Power-Down Mode

To save power, you can put the converter into low-

current shutdown mode between conversions. Two

programmable power-down modes are available:

STBYPD and FULLPD. Select STBYPD or FULLPD by

programming PD0 and PD1 in the input control byte.

When power-down is asserted, it becomes effective

only after the end of conversion. In all power-down

modes, the interface remains active and conversion

Multirange, Single +5V, 12-Bit DAS

with 12-Bit Bus Interface

______________________________________________________________________________________

13

REF

10k

2.5V

26

4.096V

4.7

µF

0.01

µF

25

REFADJ

MAX196

MAX198

Figure 9a. Internal Reference

REF

10k

2.5V

26

4.7

µF

2.5V

25

REFADJ

0.01

µF

MAX196

MAX198

4.096V

Figure 9c. The external reference overdrives the internal refer-

ence.

REF

10k

2.5V

26

4.096V

4.7

µF

25

REFADJ

MAX196

MAX198

Figure 9b. External Reference, Reference at REF