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P/N:PM0625 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.0, JUL. 01, 2005

MX10EXA

I/O PORT OUTPUT CONFIGURATION

Each I/O port pin can be user configured to one of 4

output types. The types are Quasi-bidirectional (essen-

tially the same as standard 80C51 family I/O ports),

Open-Drain, Push-Pull, and Off (high impedance). The

default configuration after reset is Quasi-bidirectional.

However, in the ROM less mode (the EA pin is low at

reset), the port pins that comprise the external data bus

will default to push-pull outputs.

I/O port output configurations are determined by the set-

tings in port configuration SFRs. There are 2 SFRs for

each port, called PnCFGA and PnCFGB, where “n” is

the port number. One bit in each of the 2 SFRs relates to

the output setting for the corresponding port pin, allow-

ing any combination of the 2 output types to be mixed

on those port pins. For instance, the output type of port

1 pin 3 is controlled by the setting of bit 3 in the SFRs

P1CFGA and P1CFGB.

Table 7 shows the configuration register settings for the

4 port output types. The electrical characteristics of each

output type may be found in the DC Characteristic table.

Table 7. Port Configuration Register Settings

PnCFGB

PnCFGA

Port Output Mode

0

0

Open Drain

0

1

Quasi-bidirectional

1

0

Off (high impedance)

1

1

Push-Pull

NOTE:

Mode changes may cause glitches to occur during tran-

sitions. When modifying both registers, WRITE instruc-

tions should be carried out consecutively.

EXTERNAL BUS

The external program/data bus allows for 8-bit or 16-bit

bus width, and address sizes from 12 to 20 bits. The bus

width is selected by an input at reset (see Reset Op-

tions below), while the address size is set by the pro-

gram in a configuration register. If all off-chip code is

selected (through the use of the EA pin), the initial code

fetches will be done with the maximum address size (20

bits).

RESET

The device is reset whenever a logic "0" is applied to

RST for at least 10 microseconds, placing a low level

on the pin re-initializes the on-chip logic. Reset must be

asserted when power is initially applied to the XA and

held until the oscillator is running.

The duration of reset must be extended when power is

initially applied or when using reset to exit power down

mode. This is due to the need to allow the oscillator time

to start up and stabilize. For most power supply ramp up

conditions, this time is 10 milliseconds.

As RST is brought high again, an exception is generated

which causes the processor to jump to the reset address.

Typically, this is the address contained in the memory

location 0000. The destination of the reset jump must be

located in the first 64k of code address on power-up, all

vectors are 16-bit values and so point to page zero ad-

dresses only. After a reset the RAM contents are inde-

terminate.

Alternatively, the Boot Vector may supply the reset ad-

dress. This happens when use of the Boot Vector is forced

or when the Flash status byte is non-zero. These cases

are described in the section “Hardware Activation of the

Boot Vector” on page 10.

SOME TYPICAL VALUES FOR A AND C:

R=100K, C=1.0uF

R=1.0M, C=0.1uF

(ASSUMING THAT THE VDD RISE TIME IS 1ms OR LESS)

XA

VDD

R

C

RESET

Figure 19. Recommended Reset Circuit