s 1000ps max. CLK to output

s SHIFT overrides HOLD, /LOAD control

s Asynchronous Master Reset

s Pin-compatible with E141

s Fully compatible with industry standard 10KH,

100K ECL levels

s Internal 75K

s Fully compatible with Motorola MC10E/100E241

s Available in 28-pin PLCC package

FEATURES

8-BIT SCANNABLE

REGISTER

The SY10/100E241 are 8-bit shiftable registers designed

for use in new, high-performance ECL systems. Unlike the

E141, the E241 features internal data feedback organized

such that the SHIFT control overrides the HOLD, /LOAD

control. Thus, the normal operations of HOLD and LOAD

can be toggled with a single control line without the need for

external gating. This configuration also enables switching

to scan mode with the single SHIFT control line.

S-IN accepts serial input data when in shift mode. Data is

accepted a set-up time before the rising edge of CLK.

Shifting is also accomplished on the rising clock edge. A

HIGH on the Master Reset pin (MR) asychronously resets

all the registers to zero.

DESCRIPTION

SY10E241

SY100E241

Rev.: C

Amendment: /1

Issue Date:

February, 1998

PIN CONFIGURATION

Pin

Function

Parallel Data Inputs

S-IN

Serial Data Input

SHIFT Control

HOLD, /LOAD Control

CLK

Clock

MR

Master Reset

Data Outputs

PIN NAMES

BLOCK DIAGRAM

TOP VIEW

PLCC

J28-1

26

27

28

1

2

3

4

18

17

16

15

14

13

12

25 24 23 22 21 20 19

5

6

789

10 11

CLK

MR

S-IN

NC

R

D

S-IN

Q

R

D

Q

R

D

Q

BITS 1-6

CLK

MR

1