ML4880CS datasheet(4/15 Pages) MICRO-LINEAR

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ML4880

FUNCTIONAL DESCRIPTION

The ML4880 converts a 5.5V to 18V input to three outputs

via two synchronous buck controllers and a flyback

controller. The two buck controllers utilize a unique

current mode PFM control architecture that generate

output voltages in the range of 2.5V to 3.5V (output A),

and 4.5V to 5V (output B). The output current is set by

external components, and can exceed 2A on each supply.

The flyback controller also uses a current mode PFM

control scheme and can be used to generate a 6V to 15V

output. Again, the output current of the flyback is

dependent on external components, and output currents

of 500mA are obtainable. Even at light loads, the PFM

architecture maintains high conversion efficiencies over a

wide range of input voltages. If it is necessary to further

extend battery life, the user can shutdown and fully

disconnect each load from the input independently.

BIAS CIRCUITS

The bias circuits are comprised of a linear regulator and a

precision voltage reference. The linear regulator produces

a supply voltage (VREG) used by the control circuits. The

VREG pin should be bypassed to GND with a 4.7µF to

µF capacitor. The precision voltage reference is used by

the feedback circuit of each controller to maintain an

accurate output voltage.

SHUTDOWN LOGIC

Each controller has a separate shutdown pin. By applying

a logic high to the appropriate pin, the transconductance

amplifier and current comparator of each controller

(shown in Figures 1 and 3) can be disabled. This prevents

switching from occurring and disconnects the load from

the input. All other circuitry within the ML4880 remains

active during shutdown.

GATE CLAMP

The gate clamp circuit provides a method of preventing

the buck regulator P-channel MOSFET switches from

accidentally turning on when the input is suddenly

switched to a higher voltage. This condition can occur

during start-up or when an adapter voltage is applied. As

shown in the block diagram, the P DRV drivers are

capacitively coupled to the gates.

Assume that P DRV is in the OFF state, or at VREG, and the

gate voltage is held at VIN through the resistor. The gate-

source voltage of the MOSFET is 0V and the switch stays

off. If a higher input voltage (VIN + 5V for example) is

suddenly applied with P DRV still in the OFF state, the

source voltage of the MOSFET would jump up to VIN +

5V, but the gate would still be at VIN. The gate-source

voltage becomes –5V and the P-channel MOSFET would

turn on even though P DRV is still in the OFF state. In

order to prevent the MOSFET from turning on, the gate

clamp circuit senses the increase in the input voltage and

pumps charge into the gate side of the coupling capacitor,

quickly charging the capacitor to the new input voltage

level.

The CLAMP pin requires a capacitor to GND in order for

the gate clamp circuit to function properly. The capacitor

value should be 1.5 to 2 times the value used for the

coupling capacitor.

BUCK CONTROLLERS

A block diagram of the buck controllers is shown in Figure

1. The circuit utilizes a constant ON-time PFM control

architecture. The circuit determines the OFF-time by

waiting for the inductor current to drop to a level set by

the feedback voltage (VFB).

Figure 1. Buck Controller Functional Diagram

OSCILLATOR/

ONE SHOT

–

1.25V

–18mV

SHOOT THRU

PROTECTION

P DRV

N DRV

ISENSE

RSENSE

VFB

VSR

TON

Rgm

CURRENT

COMPARATOR

TRANSCONDUCTANCE

AMPLIFIER

SYNCHRONOUS

RECTIFIER

COMPARATOR

VIN

CIN

COUT

VOUT

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