MT46V128M4 datasheet(10/68 Pages) MICRON

10 / 68 page

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 – Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

Figure 1

Mode Register Definition

the sequential and the interleaved burst types.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may

result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively se-

lected. All accesses for that burst take place within this

block, meaning that the burst will wrap within the block

if a boundary is reached. The block is uniquely se-

lected by A1-Ai when the burst length is set to two, by

A2-Ai when the burst length is set to four and by A3-Ai

when the burst length is set to eight (where Ai is the

most significant column address bit for a given con-

Table 1

Burst Definition

Burst

StartingColumn

Order of Accesses Within a Burst

Length

Address

Type=Sequential

Type=Interleaved

0-1

1-0

A1 A0

0-1-2-3

1-2-3-0

1-0-3-2

2-3-0-1

3-0-1-2

3-2-1-0

A2 A1 A0

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

1-0-3-2-5-4-7-6

2-3-4-5-6-7-0-1

2-3-0-1-6-7-4-5

3-4-5-6-7-0-1-2

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

5-4-7-6-1-0-3-2

6-7-0-1-2-3-4-5

6-7-4-5-2-3-0-1

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0

NOTE: 1. For a burst length of two, A1-Ai select the two-

data-element block; A0 selects the first access

within the block.

2. For a burst length of four, A2-Ai select the four-

data-element block; A0-A1 select the first access

within the block.

3. For a burst length of eight, A3-Ai select the eight-

data-element block; A0-A2 select the first access

within the block.

4. Whenever a boundary of the block is reached

within a given sequence above, the following

access wraps within the block.

figuration). The remaining (least significant) address

bit(s) is (are) used to select the starting location within

the block. The programmed burst length applies to

both READ and WRITE bursts.

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to

as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type and the start-

ing column address, as shown in Table 1.

M3 = 0

Reserved

M3 = 1

Reserved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

Valid

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

2.5

Reserved

Burst Length

CAS Latency BT

A7 A6 A5 A4 A3

A2 A1 A0

Mode Register (Mx)

Address Bus

M6-M0

M8 M7

Operating Mode

A10

A12 A11

BA0

BA1

* M14 and M13 (BA0 and BA1)

must be “0, 0” to select the

base mode register (vs. the

extended mode register).

M10

M12 M11

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