RT =

x 6.25 x 10

9

1

¨

©

§

- 110 ns

In 1-

2.5V

VIN

¨

©

§

-1

2.5

Ps + 0.25 Ps

In 1-

2.5V

48V

¨

©

§

-1

=

= 51.4

Ps

LM5035C

www.ti.com

SNVS631C – JANUARY 2010 – REVISED MARCH 2013

In addition to the PWM comparator, a Volt • Second Clamp comparator also monitors the RAMP pin. If the ramp

ramp capacitor is discharged by an internal 32

Ω discharge MOSFET controlled by the V•S Clamp comparator. If

the RAMP signal does not exceed 2.5V before the end of the clock period, then the internal clock will enable the

duration. The on-time set by the Volt • Second Clamp varies inversely to the line voltage because the RAMP

(2.5V). An example will illustrate the use of the Volt • Second Clamp comparator to achieve a 50% duty cycle

limit at 200kHz with a 48V line input. A 50% duty cycle at a 200kHz requires a 2.5µs on-time. To achieve this

maximum on-time clamp level:

(1)

paired with an 110 k

Ω to approximate the desired 51.4µs time constant. If load transient response is slowed by

Oscillator, Sync Capability

The LM5035C oscillator frequency is set by a single external resistor connected between the RT and AGND pins.

To set a desired oscillator frequency, the necessary RT resistor is calculated from:

(2)

For example, if the desired oscillator frequency is 400kHz (HO and LO each switching at 200 kHz) a 15 k

Ω

resistor would be the nearest standard one percent value.

Each output (HO, LO, SR1 and SR2) switches at half the oscillator frequency. The voltage at the RT pin is

internally regulated to a nominal 2V. The RT resistor should be located as close as possible to the IC, and

connected directly to the pins (RT and AGND). The tolerance of the external resistor, and the frequency

tolerance indicated in the Electrical Characteristics, must be taken into account when determining the worst case

frequency range.

The LM5035C can be synchronized to an external clock by applying a narrow pulse to the RT pin. The external

clock must be at least 10% higher than the free-running oscillator frequency set by the RT resistor. If the external

clock frequency is less than the RT resistor programmed frequency, the LM5035C will ignore the synchronizing

pulses. The synchronization pulse width at the RT pin must be a minimum of 15 ns wide. The clock signal should

be coupled into the RT pin through a 100 pF capacitor or a value small enough to ensure the pulse width at RT

is less than 60% of the clock period under all conditions. When the synchronizing pulse transitions low-to-high

(rising edge), the voltage at the RT pin must be driven to exceed 3.2V volts from its nominal 2 VDC level. During

the clock signal’s low time, the voltage at the RT pin will be clamped at 2 VDC by an internal regulator. The

output impedance of the RT regulator is approximately 100

Ω. The RT resistor is always required, whether the

oscillator is free running or externally synchronized.

Gate Driver Outputs (HO & LO)

The LM5035C provides two alternating gate driver outputs, the floating high side gate driver HO and the ground

referenced low side driver LO. Each driver is capable of sourcing 1.25A and sinking 2A peak. The HO and LO

outputs operate in an alternating manner, at one-half the internal oscillator frequency. The LO driver is powered

directly by the VCC regulator. The HO gate driver is powered from a bootstrap capacitor connected between HB

and HS. An external diode connected between VCC (anode pin) and HB (cathode pin) provides the high side

gate driver power by charging the bootstrap capacitor from VCC when the switch node (HS pin) is low. When the

voltage.

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