LC79451KB

No.A2223-14/38

6-1-5. SPI Write Format

In SPI interface write mode, each register data is written with the register address.

Set SPIDRW to “L” in write mode.

6-1-6. SPI Read Format

In SPI interface read mode, the register data are able to be read serially.

Set SPIDRW to “H” in read mode.

After entry of the register address, the register data can be read from DAOUT pin sync with SCL clock.

The address without the register allocation is skipped.

When the register data of each address are less than 8 bits, the data of the remaining bit are read in “0.”

In read image data, last bit is old (past) image data, and one high rank bit is new (current) image data.

6-1-7. SPI Data Transmission

SDA data is written in the latch by the falling of SCL, these data are stored in the registers by 16th rising of SCL.

CS

Register address (N)

Register data (N)

Register data (N+1)

Register data (N+2)

CS

CS

CS

•••

Register address (A) + Register data (A)

Register address (B) + Register data (B)

•••

A7

A4

A1

A6 A5

A3 A2

A0 D7

D4

D1

D6 D5

D3 D2

D0

CS

SCL

SDA

(Internal latch signal)

A7 A6 A5