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MT8981DP Datenblatt(PDF) 13 Page - Mitel Networks Corporation |
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MT8981DP Datenblatt(HTML) 13 Page - Mitel Networks Corporation |
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13 / 14 page ![]() ISO-CMOS MT8981D 2-29 † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. Processor accesses are dependent on the C4i clock, and so some timings are expressed as multiples of the C4i clock period. Figure 17 - Processor Bus AC Electrical Characteristics† - Processor Bus (Figures 11 and 17) Characteristics Sym Min Typ‡ Max Units Test Conditions 1 Chip Select Setup Time tCSS 20 0 ns 2 Read/Write Setup Time tRWS 25 5 ns 3 Address Setup Time t ADS 25 5 ns 4 Acknowledgement Delay Fast Slow t AKD 40 100 ns C L=150 pF t AKD 2.7 7.2 cycles C4i cycles 5 Fast Write Data Setup Time t FWS 20 ns 6 Slow Write Data Delay tSWD 2.0 1.7 cycles C4i cycles 7 Read Data Setup Time tRDS 0.5 cycles C4i cycles , C L= 150 pF 8 Data Hold Time Read Write tDHT 20 ns RL=1 KΩ∗, CL=150 pF tDHT 20 10 ns 9 Read Data To High Impedance tRDZ 50 90 ns RL=1 KΩ∗, CL=150 pF 10 Chip Select Hold Time tCSH 0ns 11 Read/Write Hold Time tRWH 0ns 12 Address Hold Time tADH 0ns 13 Acknowledgement Hold Time tAKH 10 60 80 ns RL=1 KΩ∗, CL=150 pF DS 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.4V 0.4V 2.4V (Read) 2.0V (Write) 0.8V (Read 0.8V (Write) CS R/W A5 DTA D7 tCSS tRWS tADS tAKD tRDS tSWD tFWS tCSH tRWH tADH tAKH tDHT * * * * tRDZ to A0 to D0 |
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