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MT9075B Datenblatt(PDF) 8 Page - Mitel Networks Corporation

Teilenummer MT9075B
Bauteilbeschribung  E1 Single Chip Transceiver
PDF  78 Pages
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Hersteller  MITEL [Mitel Networks Corporation]
Direct Link  http://www.mitel.com
Logo MITEL - Mitel Networks Corporation

MT9075B Datenblatt(HTML) 8 Page - Mitel Networks Corporation

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MT9075B
Preliminary Information
8
Functional Description
MT9075B Line Interface Unit (LIU)
Receiver
The receiver portion of the MT9075B LIU consists of
an input signal peak detector, an optional two-stage
equalizer, a smoothing filter, adaptive threshold
comparators, data and clock slicers, and a clock
extractor. Receive equalization gain can be set via
software
control
or
it
can
be
determined
automatically by the peak detectors.
The output of the receive equalizer is conditioned by
a smoothing filter and is passed on to the clock and
data slicer. The clock slicer output signal drives a
phase locked loop, which generates the extracted
clock (E2o). This extracted clock is used to sample
the output of the data comparator.
The LOS output pin (pin 61 in PLCC, pin 57 in
MQFP) is user selectable, by setting control bit LOS/
LOF (page 02H, register 13H, bit 2), to indicate a
loss of signal or loss of basic frame synchronization
condition. In addition, a status bit, LLOS (bit 4 in
page 3, register 18H) is provided to indicate the
presence of a loss signal condition. The occurrence
of a loss signal condition is defined as per I.431, i.e.,
when the incoming signal amplitude is more than 20
dB below the nominal amplitude for a time duration
of at least 1 ms.
The receive LIU circuit requires a terminating
resistor of either 120
Ω or 75Ω across the device side
of the receive1:1 transformer as shown in Figure 4.
The return loss of the receiver, complying with
G.703, is greater than:
12 dB from 51 kHz to 102 kHz;
18 dB from 102 kHz to 2048 kHz;
14 dB from 2048 kHz to 3072 kHz.
The jitter tolerance of the MT9075B clock extractor
circuit exceeds the requirements of G.823 (Figure 3).
Transmitter
The MT9075B differential line driver is designed to
drive a 1:2 step-up transformer (see Figure 4). A
0.68 uF capacitor is required between the TTIP and
the transmit transformer. Resistors RT (as shown in
Figure 4) are for termination for transmit return loss.
The values of RT may be optimized for 120Ω lines,
75
Ω lines or set at an intermediary value to serve
both applications. Program the Transmit Pulse
Control Word (address 1FH page 1) to adjust the
pulse amplitude accordingly. Alternatively, the pulse
level and shape may be discretely programmed by
writing to the Customer Pulse Level registers
(addresses 1CH to 1FH, page 2) and setting the
Custom Transmit Pulse bit high (bit 3 of the Transmit
Pulse Control Word).
Figure 3 - Typical Jitter Tolerance
18UI
1.5UI
0.2UI
1.667Hz
20Hz
2.4kHz 18kHz 100kHz
Peak to Peak
Jitter Amplitude
(log scale)
Jitter Frequency
(log scale)
MT9075B
Tolerance



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