VP520S

6

using fast page mode in order to guarantee RAS precharge

times and RAS to CAS delays.

The above time partitioning gives a line rate of 6.75 MHz,

which meets real time CIF requirements. The exchange rate

with the encoder or decoder is only half of this, but is adequate

for CIF data at 30 Hz frame rates. In the decode mode the

VP520S produces two fields at 60 Hz rates from every 30 Hz

received frame, thus writing need only be half the rate of

reading. In the decimate mode the VP520S produces a CIF

frame using line rates which could have supported two 60Hz

fields, but only one is used. Thus reading rates need only be

half writing rates since the spare field time is available.

In the interpolate mode two complete CIF frame stores are

required, which dictates the use of 256K word DRAM's. The

A8 pin then provides the ninth address bit needed for such

devices. In the decimate mode only one CIF frame store is

required, and a Control Register Bit allows the user to select

either 256K word DRAM's, or 64K x 16 devices. In the latter

case two such devices are needed, and the A8 pin now

supplies a second CAS strobe to enable the second device.

Refresh cycles generate CAS before RAS sequences.

HOST INTERFACE

The VP520S employs a conventional memory mapped

host interface using a data bus and an address bus. To

minimize on pin count the VP520S only uses four address

lines, and all internal RAM is addressed through counters. All

data is validated with a read or write strobe, and an active low

enabling signal. These strobes can be asynchronous to the 27

MHz clock, but the latter must be present to move the data

through several pipeline delays. Strobes must thus be valid for

several clock periods. Timing is shown in Figure 5.

In the worst case mode ( QCIF to NTSC video ), the device

must store 40 horizontal coefficients and 210 vertical coeffi-

cients. Internal storage must thus be provided for a total of 250

eight bit coefficients, and this is split into four blocks. These

consist of storage for 24 horizontal luminance coefficients;

storage for 16 horizontal chrominance coefficients; storage for

70 vertical luminance coefficients; and finally 140 vertical

chrominance coefficients. Each block of RAM has its own

internal address counter, and all counters are simultaneously

reset with a write to address F hex. Each RAM area has an

associated address as listed below, and a read or write using

that address will increment the relevant counter. Attempts to

use more addresses than are applicable to a particular area

will cause undefined behaviour.

Address allocations are given below;

Addr

Function

0

Reserved

1

R/W horizontal luminance coefficients. Max 24

2

R/W horizontal chrominance coefficients. Max 16.

3

Normally 00 Hex. When 02 Hex the sync generator can be

reset with the FRST and VRST pins.

4

Reserved for internal use

5

R/W vertical luminance coefficients. Max 70.

6

R/W vertical chrominance coefficients. Max 140.

7

Set to the normal operating value of 01 Hex by RESET. When

loaded with 21 Hex an encoding plus a decoding VP520S can

be connected 'back to back' for test purposes or coefficient

investigations. No other values must be used.

8

Control Register 0. See below.

9

Control Register 1. See below

A

Line delay from VREF to first active line. 6MSBs only

A/B

Pixel delay from HREF to first active pixel 2 Bits from A

plus 8 from B to give a 10 Bit value. Bit A1 is the MSB

C

Blanked screen Y value

D

Blanked screen U value

E

Blanked screen V value

F

Clear all address counters

The bits in control registers 0 and 1 are used individually,

and are defined below. Where necessary the action caused

when changing a control bit is delayed until the start of a new

field.

REGISTER 0 (Address 8)

BIT

FUNCTION

0

Interpolate if high, decimate if low

1

PAL if low, NTSC if high

2

QCIF if high, CIF if low

3

If low subtract 16 from Y, add 16 back after filtering

4

If low subtract 128 from chrominance I/Ps, add 128 to O/Ps

5

If low generate sync, if high lock to HREF and VREF

6

If low then active edge of VREF is low going.

7

If low then active edge of HREF is low going.

REGISTER 1 (Address 9)

BIT

FUNCTION

0

If low then U inputs precede V inputs and outputs

1

If low use the internal field detect logic

2

Field Select. See text.

3

If low use 64Kx16 DRAM ( encoder only )

4

When high specifies Split Screen mode (encoder only)

5

When low the Frame Ready Flag is enabled

6

When high the screen is blanked (colour defined in addresses

C, D, E)

7

When high DRAM writes are disabled

USE OF ADDRESS 7

By loading Hex 21 into host address 7 it is possible to

connect the encoding and decoding filters into a back to back

configuration. This is useful for test purposes or for evaluating

the filter coefficient values, and it avoids the need for a 'Frame

Start' signal into the filter in the decode path. In normal

operation address 7 should contain 01 which is the default

after a reset operation.

LOADING COEFFICIENTS

The following tables show the coefficient storage locations

for different modes. The filter sections below describe the use

of coefficient sets. Within a set, coefficients are stored in

ascending order, ie. C0, C1, C2 etc. Note that some locations

are shown as not used. However, since each store is loaded

sequentially, the data stream used to load the coefficient

stores must contain padding values corresponding to the

unused addresses. Note also that only the address range

shown in the tables have to be loaded with data.