WAFER LEVEL PACKAGING

Data Sheet

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Wafer Level Processing &

Die Processing Services (WLP/DPS)

Amkor offers Wafer Level Chip Scale Packaging (WLCSP)

providing a solder interconnection directly between a device

and the motherboard of the end product. WLCSP includes

wafer bumping (with or without pad layer redistribution or

RDL), wafer level final test, device singulation and packing

in tape & reel to support a full turnkey solution. Amkor’s

robust Under Bump Metallurgy (UBM) over PBO or PI

dielectric layers on the die active surface providing a

reliable interconnect solution able to survive harsh board

level conditions meeting the demands of the growing global

consumer market place for portable electronics.

Fueling Growth

• Small packages in mobile are critical to maximize

battery size

• Level of adoption in fastest growing markets

(i.e., tablets and smartphones)

• Dis-integration of high performance functions from

processors to new specialized devices(e.g., audio)

• Fewer cycles through electrical test

• Lower cost to EMS assembly MSL L1 package from T&R

• Improved SMT-compatible underfill processes at EMS

companies increase prior die size limits

a reliable, cost-

effective, true chip

size package on

devices not requiring

redistribution. The

BoR option utilizes a

repassivation polymer layer with excellent electrical/

mechanical properties. A UBM is added, and solder bumps

are then placed directly over die I/O pads. CSPnl is

designed to utilize industry-standard surface mount

assembly and reflow techniques.

DS720H

Rev Date: 1/16

WLCSP

option adds a plated copper

Redistribution Layer (RDL) to route I/O

pads to JEDEC/EIAJ standard pitches,

avoiding the need to redesign legacy

parts for CSP applications. A nickel-

based or thick copper UBM offerings, along with polyimide or PBO

dielectrics, provide best in class board level reliability performance. CSPnl

with RDL utilizes industry-standard surface mount assembly and reflow

techniques, and does not require underfill on qualified device size and I/O

layouts.

copper for both redistribution and

UBM. This simplified process flow

reduces cost and cycle time by over

20%. CSPn3 has been in production

since 2009 and as of 2015 has a run

rate of over 2.8 billion units since its introduction.

Applications

The WLCSP package family is applicable for a wide range of semiconductor

device types from high end RF WLAN combo chips, to FPGAs, power

management, Flash/EEPROM, integrated passive networks and standard

analog. WLCSP offers the lowest total cost of ownership enabling higher

semiconductor content while leveraging the smallest form factor and one of

the highest performing, most reliable, semiconductor package platforms on

the market today. WLCSP is ideally suited for, but not limited to, mobile

phones, tablets, netbook PCs, disk drives, digital still & video cameras,

navigation devices, game controllers, other portable/remote products and

some automotive end applications.

Wafer Level Features

• 4-196 ball count

• PBO & Polyimide (PI) Repassivation and Redistribution Layer (RDL)

available

• Electroplated Sn/Ag < 0.3 µm and SAC Alloy ball-loaded bumping options

≥ 0.3 µm pitch

• Reliable thick Cu UBM or Ni/Au for best in class EM performance

• Compatible with conventional SMT assembly and test techniques

Die Level Features

• Best in class component and board level reliability

• JEDEC tested board level performance demonstrated without underfill

• Precision edge quality ensuring device integrity at board mount

• Back-side laminate coating available

• Cost effective T&R packaging solutions for small ICs

• Ultra-thin backgrinding for embedded die applications

• Full turnkey WLP, contact probe and DPS supported in Taiwan, China and

Korea

• Wide selection of pocket tape carrier options