1

2

6

5

LMP7300

HYSTP

HYSTN

-

+

4

HYSTN

TP3

JP4

JP3

HYSTP

TP2

JP2

JP1

TP1

R2

1 M:

R1

1 M:

J3

J2

C1

0.1 PF

C2

OPEN

5 PF

R9

1 M:

VCC

VOH

OUT

BNC

TP4

VREF

JP5

JP6

R7

50 k:

R10

1 M:

R6

50 k:

R5

1 M:

C4

0.1 PF

C6

OPEN

5 PF

VEE

VOH

VCC

GND

VEE

J4

J5

J6

J1

VOH

VCC

VEE

R3

OPEN

TP5

R8

OPEN

CREF

OPEN

VIN

BNC

R4

50 k:

LMP7300

SNOSAT7G – AUGUST 2007 – REVISED OCTOBER 2015

www.ti.com

10 Layout

10.1 Layout Guidelines

A good PCB layout is always important to reduce output to input coupling. Positive feedback noise reduces

performance. For the LMP7300, output coupling is minimized by the unique package pinout. The output is kept

away from the noninverting and inverting inputs, the reference and the hysteresis pins.

10.2 Layout Example

The following section shows an example schematic and layout for the LMP7300MA 8-pin SOIC package.

Figure 27. LMP7300MA-EVAL Schematic

20

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