USB4624 datasheet(51/58 Pages) MICROCHIP

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USB 2.0 HSIC Hi-Speed 4-Port Hub Controller

Datasheet

 2014 Microchip Technology Inc.

DS00001717A-page 51

9.5.2

Reset and Configuration Strap Timing

Figure 9.2 illustrates the RESET_N timing requirements and its relation to the configuration strap

signals. Assertion of RESET_N is not a requirement. However, if used, it must be asserted for the

minimum period specified.

Refer to Section 8.4, "Resets," on page 42 for additional information on resets. Refer to Section 6.3,

"Device Configuration Straps," on page 30 for additional information on configuration straps.

9.5.3

USB Timing

All device USB signals conform to the voltage, power, and timing characteristics/specifications as set

forth in the Universal Serial Bus Specification. Please refer to the Universal Serial Bus Specification,

Revision 2.0, available at http://www.usb.org.

9.5.4

HSIC Timing

All device HSIC signals conform to the voltage, power, and timing characteristics/specifications as set

forth in the High-Speed Inter-Chip USB Electrical Specification. Please refer to the High-Speed Inter-

Chip USB Electrical Specification, Version 1.0, available at http://www.usb.org.

9.5.5

SMBus Timing

All device SMBus signals conform to the voltage, power, and timing characteristics/specifications as

set forth in the System Management Bus Specification. Please refer to the System Management Bus

Specification, Version 1.0, available at http://smbus.org/specs.

9.5.6

I2C Timing

All device I2C signals conform to the 100KHz Standard Mode (Sm) voltage, power, and timing

characteristics/specifications as set forth in the I2C-Bus Specification. Please refer to the I2C-Bus

Specification, available at http://www.nxp.com.

Figure 9.2 RESET_N Configuration Strap Timing

Table 9.9 RESET_N Configuration Strap Timing

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

trstia

RESET_N input assertion time

tcsh

Configuration strap hold after RESET_N deassertion

RESET_N

Configuration

Straps

trstia

tcsh

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