USB5537B datasheet(15/79 Pages) MICROCHIP

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 2012 - 2015 Microchip Technology Inc.

DS00001682C-page 15

USB5537B

4.1.3

32-BYTE CACHE

There is a 32-byte pipeline cache, and associated with the cache is a base address pointer and a length pointer. Once

the SPI controller detects a jump, the base address pointer is initialized to that address. As each new sequential data

byte is fetched, the data is written into the cache, and the length is incremented. If the sequential run exceeds 32 bytes,

the base address pointer is incremented to indicate the last 32 bytes fetched. If the USB5537B does a jump, and the

jump is in the cache address range, the fetch is done in 1 clock from the internal cache instead of an external access.

4.1.4

INTERFACE OPERATION TO SPI PORT WHEN NOT DOING FAST READS

There is an 8-byte command buffer: SPI_CMD_BUF[7:0]; an 8-byte response buffer: SPI_RESP_BUF[7:0]; and a length

ber of clocks. After the first byte, the COMMAND, has been sent out, and the SPI_DI is stored in the SPI_RESP buffer.

If the SPI_CMD_LEN is longer than the SPI_CMD_BUF, don’t cares are sent out on the SPI_DO line. This mode is used

for program execution out of internal RAM or ROM.

FIGURE 4-4:

SPI DUAL HI-SPEED READ SEQUENCE

FIGURE 4-5:

SPI INTERNALLY-CONTROLLED OPERATION

SPI_CEN

SPI_CLK

SPI_DO

SPI_DI

MSB

HIGH IMPEDANCE

15 16

12 3 4

ADD.

23 24

ADD.

39 40

31 32

47 48

51 52

55 56

NN+1

N+2

N+3

N+4

MSB

N+1

N+2

N+3

N+4

MSB

Bits-7,5,3,1

Bits-6,4,2,0

Bits-7,5,3,1

Bits-6,4,2,0

SPI

CONTROLLER

SPI

ROM

SPI_RSP_BUF[7:0]

SPI_CMD_BUF[3:0]

SPI_CMD_LEN

CE#

CLK

USB Hub

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