STGIPS40W60L1

Electrical characteristics

Doc ID 018866 Rev 3

13/21

3.1.2

Dead time

Figure 8.

Typical dead time vs. DT resistor value

Figure 7.

Dead time and interlocking waveforms definitions

LIN

HIN

LVG

HVG

LIN

HIN

LVG

HVG

LIN

HIN

LVG

HVG

LIN

HIN

LVG

HVG

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

CONTROL SIGNAL EDGES

OVERLAPPED:

INTERLOCKING + DEAD TIME

CONTROL SIGNALS EDGES

SYNCHRONOUS (*):

DEAD TIME

CONTROL SIGNALS EDGES

NOT OVERLAPPED,

BUT INSIDE THE DEAD TIME:

DEAD TIME

CONTROL SIGNALS EDGES

NOT OVERLAPPED,

OUTSIDE THE DEAD TIME:

DIRECT DRIVING

(*) HIN and LIN can be connected together and driven by just one control signal

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

0

0.5

1

1.5

2

2.5

3

3.5

0

50

100

150

200

250

300

Rdt (kOhm)

AM06020v1