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54F258ADM Datenblatt(PDF) 2 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Teilenummer 54F258ADM
Bauteilbeschribung  Quad 2-Input Multiplexer with TRI-STATE Outputs
PDF  8 Pages
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Hersteller  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

54F258ADM Datenblatt(HTML) 2 Page - National Semiconductor (TI)

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Unit LoadingFan Out
54F74F
Pin Names
Description
UL
Input IIH IIL
HIGHLOW
Output IOH IOL
S
Common Data Select Input
1010
20 mA b06 mA
OE
TRI-STATE Output Enable Input (Active LOW)
1010
20 mA b06 mA
I0a–I0d
Data Inputs from Source 0
1010
20 mA b06 mA
I1a–I1d
Data Inputs from Source 1
1010
20 mA b06 mA
Za–Zd
TRI-STATE Inverting Data Outputs
15040 (333)
b
3 mA24 mA (20 mA)
Functional Description
The ’F258A is a quad 2-input multiplexer with TRI-STATE
outputs It selects four bits of data from two sources under
control of a common Select input (S) When the Select input
is LOW the I0x inputs are selected and when Select is
HIGH the I1x inputs are selected The data on the selected
inputs appears at the outputs in inverted form The ’F258A
is the logic implementation of a 4-pole 2-position switch
where the position of the switch is determined by the logic
levels supplied to the Select input The logic equation for
the outputs is shown below
Zn e OE  (I1n  S a I0n  S)
When the Output Enable input (OE) is HIGH the outputs are
forced to a high impedance OFF state If the outputs of the
TRI-STATE devices are tied together all but one device
must be in the high impedance state to avoid high currents
that would exceed the maximum ratings Designers should
ensure that Output Enable signals to TRI-STATE devices
whose outputs are tied together are designed so there is no
overlap
Truth Table
Output
Select
Data
Output
Enable
Input
Inputs
OE
SI0
I1
Z
H e HIGH Voltage Level
L e LOW Voltage Level
HX
X
X
Z
X e Immaterial
LH
X
L
H
Z e High Impedance
LH
X
H
L
LL
L
X
H
LL
H
X
L
Logic Diagram
TLF9508 – 4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2



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